Instruction Format for Different Addressing Modes

Learning Outcome:

Understand instruction formats for different addressing modes and implement an instruction life-cycle.

Tasks:

Define instruction formats for immediate, direct, register, and indirect addressing.

Simulate instruction fetch-decode-execute-write back cycle.

Description:

Register Addressing Mode: An Efficient Operand Access Method

Register addressing mode is a technique where instructions directly specify registers, rather than memory addresses, to access operands. The opcode in the instruction defines the operation to be performed, while the operand field identifies the registers involved. Since data is accessed from registers—high-speed storage units within the processor—this mode is highly efficient, eliminating the delays associated with slower memory access. However, its effectiveness is constrained by the limited number of available registers.

Key Features

1. Efficient Data Access: Operands are accessed directly from registers, ensuring minimal latency.

2. High Speed: Eliminates memory access delays, accelerating computation.

3. Limited Scope: Constrained by the finite number of registers available in the processor.

Workflow of Register Addressing Mode

1. Program Counter Initialization

• The Program Counter (PC) is initialized to point to the start of the program in the code memory (typically ROM).

• Initialization is managed by the PC Initialize Module.

2. Instruction Fetch

1. The PC sends the current instruction address to the Memory Address Register (MAR).

2. The instruction at the specified address is read from Code Memory and temporarily stored in the Memory Buffer Register (MBR).

3. The instruction is transferred from the MBR to the Instruction Register (IR) for further processing.

3. Instruction Decode

1. The Instruction Register (IR) holds the fetched instruction.

2. The Decode Unit processes the instruction by splitting it into:

   • Opcode (OP): Specifies the operation (e.g., ADD, SUB, MOVE).

   • Operands: Identify the registers involved in the operation.

3. In register addressing mode, the operand field directly specifies the registers to be accessed.

4. Operand Fetch

• If the instruction requires data:

  • The specified registers (e.g., RA and RB) are accessed based on the operand field.

  • Data from these registers is sent to the ALU or other functional units for processing.

5. Execution

• The processor performs the operation defined by the opcode. Common examples include:

  • LOAD: Transfer data between registers.

  • Arithmetic/Logical Operations: The ALU performs computations (e.g., addition, subtraction) using data from RA and RB and stores the result in RZ.

6. Write Back

• For certain instructions (e.g., MOVE, ADD):

  • The result stored in RZ is written back to the target register specified in the instruction.

Advantages of Register Addressing Mode

• Speed: Data is accessed directly from registers, significantly reducing latency.

• Efficiency: Suitable for operations requiring frequent data manipulation.

• Simplified Instruction Execution: By avoiding memory access, the CPU focuses on faster register-based operations.

Conclusion

Register addressing mode ensures rapid and efficient instruction execution by leveraging high-speed register access. Its streamlined workflow—from instruction fetch to write-back—minimizes delays and optimizes performance. While the finite number of registers limits its scope, this mode remains a cornerstone of efficient processor design for tasks requiring high-speed data manipulation.

Deliverables:

Logisim files can be accessed from here:

(to be downloaded and opened through logisim)

Reference Images: