Special Function Registers

Learning Outcomes:

Design a register file to store processor states and special function registers for specific control operations. 

Tasks:

Design and implement special function registers (SFRs) such as PC, IR, MAR, MDR

Explore context switching scenarios.

Description:

Special Function Register (SFR) 

Special Function Registers (SFRs) are special memory addresses in microcontrollers that control and monitor hardware operations. They are hardware interfaces and also play a central role in several operations, such as: 

1. I/O operations

2. Timer control 

3. Interrupt management 

4. Serial communication

This enables a microcontroller to seamlessly interface with external peripherals as well as schedule actual-time activities by adjusting the setting of the SFRs.

Instruction Processing Keystroke Registers 

1. Program Counter: (PC):

  • Is holding the address for the next instruction for the computer in sequence for that program

  • Shows control what should go where as they determine that

2. Instruction Register: (IR):

Keeps the instruction being executed in memory, once fetched.  It acts as the key component of decoding and executing the instruction.

3. Memory Address Register (MAR): 

Contains the memory address where data or instructions to be retrieved will be found.

Bridges between the CPU and memory while doing a fetch or write.

4. Memory Buffer Register (MBR):

Temporarily holds the data transferred from/to memory to/from the CPU.  

It serves as a buffer, thus, smoothing the data transfer in both the read and write cycles.

How these Registers work together

The coordinated functioning of these registers enables the CPU to process instructions efficiently through the following steps:  

1. Fetch:  

   - The PC sends the address of the next instruction to the MAR.  

   - The instruction is fetched from memory, stored in the MBR, and then transferred to the IR.  

2. Decode:

- The control unit decodes the instruction in the IR and identifies the operation and data that must be acquired.

3. Execute:

- Execute the decoded instruction, which could access memory via the MAR and MBR.

This smooth collaboration ensures that the instructions are correctly executed and that the system works as expected.

Deliverables:

Logisim files can be downloaded here

Program Counter

Reference Images