Activity Learning

Problem Statement:

Design the instruction cycle for an 8-bit processor using a 2-address format in register addressing mode 

Description:

Overview of an 8-Bit Processor with 2-Address Format and Register Addressing Mode

An 8-bit processor using a 2-address instruction format and register addressing mode operates by directly specifying two registers in each instruction. The source register provides the operand, while the destination register stores the result. This approach eliminates the delays associated with memory access, enabling faster execution by leveraging the processor's registers for immediate data access.

Instruction Format

• Instruction Width: 8 bits

• Opcode: 4 bits (Specifies the operation)

• Source Register (SRC): 2 bits (Specifies the register containing the operand)

• Destination Register (DEST): 2 bits (Specifies the register to store the result)

Example Instruction Format:

[ Opcode (4 bits) | SRC (2 bits) | DEST (2 bits) ]

Instruction Cycle

1. Fetch Phase

The instruction is retrieved from memory using the address stored in the Program Counter (PC). After fetching, the PC is incremented to point to the next instruction in memory.

Microoperations:

1. MAR ← PC

2. IR ← MEMORY[MAR]

3. PC ← PC + 1

2. Decode Phase

The fetched instruction in the Instruction Register (IR) is decoded. This involves extracting the opcode, source register (SRC), and destination register (DEST) fields.

Microoperations:

1. OP ← IR[7:4]

2. SRC ← IR[3:2]

3. DEST ← IR[1:0]

3. Execute Phase

The processor performs the operation specified by the opcode using the data from the source register. The result is then written to the destination register.

Microoperation:
R[DEST] ← ALU(OP, R[SRC])

Example Operation: ADD R1, R2

Instruction Details:

• Opcode: ADD (e.g., 0001)

• Source Register (SRC): R1 (e.g., 01)

• Destination Register (DEST): R2 (e.g., 10)

Binary Representation of Instruction:

0001 01 10

Execution Steps:

1. Fetch:
   The instruction 0001 01 10 is retrieved from memory.

2. Decode:

   • Opcode = ADD

   • SRC = R1

   • DEST = R2

3. Execute:

   • Perform the operation: R2 ← R2 + R1

Conclusion

The 8-bit processor with a 2-address format and register addressing mode achieves efficient operation by minimizing memory access. By operating directly on registers, it significantly reduces memory overhead and ensures faster execution of register-to-register operations. This design is particularly advantageous for tasks requiring high-speed data manipulation.

Deliverables:

Logisim files can be accessed from here:

(to be downloaded and opened through logisim)

Reference Images: