Oxide-based two-terminal memristors serve a dual purpose by not only storing data within their analog conductance states but also processing data at the same physical locations. This unique capability enables highly efficient computing, both in-memory and in parallel. Our focus revolves around the design, integration, and thorough characterization of cutting-edge nanoelectronic devices tailored for the field of neuromorphic computing. 

Phase-change memory (PCM) is a cutting-edge non-volatile memory technology based on the rapid and reversible phase transition between the amorphous and crystalline states of specific phase-change materials. This distinctive property of PCM, which allows for precise control of conductance levels, positions it as an ideal candidate for implementing synaptic functions in neuromorphic computing and memory applications.

The two-terminal Ovonic Threshold Switch (OTS) device has received extensive research attention, particularly for its application as a selector. This is primarily because it offers high current density for effectively programming and erasing memory elements when in the ON state. Moreover, it exhibits low leakage current when in the OFF state, making it ideal for preventing parasitic sneak currents in unselected cells within cross-bar arrays. One notable application of this technology is the implementation of Phase-Change Memory (PCM) with OTS elements, often referred to as PCMS. This approach has been put into practice by Intel, particularly for high-density memory applications, further underscoring the significance of the OTS device in advanced memory technology.

Our research is centered on the development of a fully integrated, reprogrammable memristor chip. This chip includes a passive memristor crossbar array seamlessly integrated with all essential interface circuitry, digital buses, and a processor, creating a comprehensive neuromorphic hardware system-on-chip. 

The memristor array's exceptional high density and non-volatile characteristics enable the on-chip storage of entire Deep Neural Network (DNN) models. This effectively eliminates the inefficiencies associated with off-chip memory access, leading to the promise of significantly improved energy efficiency in DNN operations.