This project focuses on the development of a hybrid neural-network accelerator that integrates Digital In-Memory Computing (DIMC) with energy-efficient array processors to enable high-performance edge-AI inference under low-voltage operation. By combining the computational density of DIMC with the flexibility and programmability of array-based processing, the architecture balances speed, accuracy, and power efficiency. The hybrid design supports aggressive voltage scaling while maintaining reliable performance, significantly reducing energy per operation. This work advances next-generation edge-AI hardware by delivering a compact, scalable, and energy-optimized accelerator suitable for wearables, IoT nodes, and other power-constrained intelligent systems.

This project aims to advance AI-driven methodologies for predicting, analyzing, and optimizing CMOS analog and RF circuit behavior. By developing a sequential prediction framework, the work enables multi-parameter performance estimation where each predicted output is iteratively incorporated to enhance the accuracy of subsequent predictions. This approach closely mirrors real circuit dependencies, resulting in more reliable modeling of complex analog/RF designs. Additionally, the project focuses on improving explainability in circuit prediction, ensuring that AI-generated insights are transparent, interpretable, and meaningful for circuit designers. Together, these contributions support faster design-space exploration, reduced simulation cost, and smarter decision-making in modern CMOS circuit development.

Our project pioneers the design of cutting-edge dynamic comparators to significantly boost the performance of SAR ADCs in convolutional neural networks and in-memory computing. These comparators feature a rail-to-rail input common-mode range with common-mode insensitivity, ensuring superior SNR for SAR ADCs. Key specifications include rail-to-rail input common-mode range, high energy efficiency and minimal kickback noise. Comprehensive validation—encompassing transient noise analysis, Monte Carlo simulations, and process-Vdd-temperature corner tests—guarantees robust performance and low offset. These innovative designs have undergone silicon validation in UMC 180 nm, with technology node scaling effects verified for the 28 nm technology node. 

This project focuses on advanced dynamic comparators and analog-to-digital converters (ADCs) to achieve high-speed, high-precision, and low-power performance. Our innovative designs feature a versatile self-calibration logic circuit that is agnostic to the offset calibration technique utilized and fits like a perfect puzzle to all techniques with significantly reducing input-referred offset, making them ideal for high-speed flash and asynchronous SAR ADCs. We introduce a 6-bit, 1 GS/s flash ADC with a novel offset correction technique in 65-nm CMOS technology, achieving excellent signal-to-noise and distortion ratios and spurious-free dynamic range with minimal power consumption. Additionally, we propose a time-domain bulk-tuned offset cancellation technique for dynamic comparators, drastically reducing offset while maintaining low power usage and high operational frequency.