Our project pioneers the design of cutting-edge dynamic comparators to significantly boost the performance of SAR ADCs in convolutional neural networks and in-memory computing. These comparators feature a rail-to-rail input common-mode range with common-mode insensitivity, ensuring superior SNR for SAR ADCs. Key specifications include high energy efficiency and minimal kickback noise. Comprehensive validation—encompassing transient noise analysis, Monte Carlo simulations, and process-Vdd-temperature corner tests—guarantees robust performance and low offset. These innovative designs have undergone silicon validation in UMC 180 nm, with technology node scaling effects verified for the 28 nm technology node. 

This project focuses on advanced dynamic comparators and analog-to-digital converters (ADCs) to achieve high-speed, high-precision, and low-power performance. Our innovative designs feature a versatile self-calibration logic circuit that is agnostic to the offset calibration technique utilized and fits like a perfect puzzle to all techniques with significantly reducing input-referred offset, making them ideal for high-speed flash and asynchronous SAR ADCs. We introduce a 6-bit, 1 GS/s flash ADC with a novel offset correction technique in 65-nm CMOS technology, achieving excellent signal-to-noise and distortion ratios and spurious-free dynamic range with minimal power consumption. Additionally, we propose a time-domain bulk-tuned offset cancellation technique for dynamic comparators, drastically reducing offset while maintaining low power usage and high operational frequency.