Abstract: Magnesium (Mg) alloys are increasingly used in biomedical applications due to their biodegradability, biocompatibility, and mechanical compatibility with human bone. However, fabricating these alloys using additive manufacturing techniques like Selective Laser Melting (SLM) is challenging due to their high reactivity and the potential for internal defects such as gas porosity and lack of fusion. This study presents a comprehensive evaluation of deep learning-based image segmentation methods for detecting such defects in Mg-based alloys fabricated via SLM at 80 W laser power and 500 mm/s scanning speed. X-ray Computed Tomography (XCT) was used to scan the printed samples, and 83 non-identically distributed image slices were selected to ensure variation in defect morphology. Two types of annotations—manual (using LabelImg) and threshold-based (using ImageJ)—were used to prepare datasets. These datasets were analyzed using two models: a custom U-Net with five-fold cross-validation and a U-Net with ResNet-50 backbone enhanced by patchify augmentation. The threshold-based dataset combined with U-Net + ResNet50 achieved the highest segmentation accuracy with an IoU of 86%, outperforming manual annotation-based training. This study emphasizes the importance of annotation strategy and model selection in defect detection workflows for reactive metal additive manufacturing.

Abstract: The integration of Large Language Models (LLMs) into materials and manufacturing offers a transformative approach to achieving ISO 9001 -compliant product quality, aligning with the goals of Industry 5.0. This work proposes MatManQ (Large Language Model in Material and Manufacturing for Product Quality and Control), a framework that leverages LLMs for quality control, assurance, and agentic AIdriven decision-making. A case study on alloy behavior using a self-curated dataset demonstrates the framework's capabilities. Five open-source LLMs-Mixtral-8x7B-327, TinyLlama-1.1B, deepset/roberta, Gemini, and FLAN-T5-were fine-tuned using a Retrieval-Augmented Generation (RAG) approach. Mixtral-8x7B-327 achieved the highest F1 score of 92.1%, attributed to its sparse Mixture-of-Experts architecture, enabling precise and efficient reasoning. The study highlights the potential of LLMs to unify material and manufacturing insights for enhanced product quality, while outlining key challenges and future directions for industrial deployment.

Abstract: A conceptual framework, I-AMS-IC (Intelligent Analog and Mixed-Signal IC), is proposed to enable automation in analog/mixed-signal (AMS) design by integrating machine learning with an emphasis on interpretability and trustworthiness. The framework is demonstrated using a custom-built dataset based on an operational amplifier (Op-Amp) case study. Machine learning models are trained to predict design variables from ten key performance indicators (KPIs). The relationships between design variables and performance metrics are explored using various correlation analysis methods. Among the models tested, XGBoost regression achieves the best performance with a mean absolute percentage error (MAPE) of 16.88%. To enhance interpretability, SHAP (Shapley Additive Explanations) is employed to explain model predictions. The SHAP insights are validated through both correlation analysis and analytical circuit expressions. The study highlights that combining statistical, analytical, and explainability techniques strengthens trust and transparency in AI-assisted AMS design, paving the way for more interpretable and automated design workflows.

Abstract: This paper presents a high-speed, low kickback noise dynamic comparator featuring a modified three-stage architecture that demonstrates rail-to-rail input common-mode voltage (Vi,cm) operation. The proposed design utilizes parallel NMOS and PMOS pre-amplifier signal paths, which feed into a modified Strong-Arm latch. To ensure high-speed performance across the full 0-Vdd Vi,cm range, a PMOS pre-amplifier and two-stage NMOS pre-amplifier are employed. The additional amplification stage between the NMOS pre-amplifier and the latch allows the use of NMOS input pairs in latch for NMOS pre-amplification stage as well. This architecture enhances Vi,cm range and also improves kickback noise immunity by leveraging the complementary noise contributions of the NMOS and PMOS signal paths. The proposed comparator maintains Vi,cm insensitivity and robust speed performance throughout the entire Vi,cm range. Fabricated in 180-nm CMOS technology, the prototype achieves a relative CLK-Q delay of less than 210 ps and an energy-delay product (EDP) below 86 fJ·ns, for 1.8V supply.

Abstract: A low-power, high-speed dynamic comparator with the addition of a cross-coupled pair in the pre-amplifier stage, followed by a strong-arm latch, is presented. The proposed modification increases the pre-amplifier's differential and common-mode gains, improving the latch's differential and common-mode input voltage, resulting in faster regeneration with 22% speed improvement as compared to conventional comparator at small input differential voltages ( Vi,id ). The proposed technique boosts the comparator's speed and helps achieve 21% lower energy per conversion delay product (EDP) compared to the literature. Analytical modeling of the delay that proves the improvement in the speed of the proposed comparator is also presented and verified with the simulation results. The proposed comparator's delay is insensitive to the common-mode voltage ( Vi,cm ). The proposed comparator is fabricated in 180-nm CMOS technology and measurement shows less than 160ps relative CLK-Q delay with 81 fJ.ns EDP and 0.8mV input-referred rms noise with 1.8V supply. To demonstrate the scalability of the proposed technique to advanced technology nodes, the proposed design is also simulated in 65-nm CMOS technology with a 1.1V supply for 5GHz frequency. For Vi,cm of 0.3V and Vi,id of 1mV and 10mV, the proposed comparator exhibits a 40.69ps and 32.41ps delay and has 3.74 fJ.ns and 2.78 fJ.ns EDP respectively.

Abstract: This paper presents a low-power, high-speed dynamic comparator with a rail-to-rail input common-mode (Vi,cm) range. The proposed comparator has high-speed performance throughout the 0-Vdd Vi,cm range, thus attributing common-mode insensitivity. This work introduces a merger of NMOS and PMOS dynamic pre-amplifiers with a modified latch to achieve the rail-to-rail Vi,cm operation. A novel activation clock logic is also proposed, activating only one pre-amplifier based on the Vi,cm value and ensuring low-power consumption and provides reduction of 17% in the energy per conversion as compared to the comparator without activation clock logic. The proposed comparator is designed using 65-nm CMOS technology with a 1.2 V supply voltage and is operating at 1 GHz frequency. We have presented the analytical models of the delay and offset which is verified with the rigorous post-layout simulation results. To validate the robustness of the proposed comparator, the PVT corner analysis with Monte Carlo simulation is also performed for different Vi,cm.

Abstract: This paper proposes a novel asynchronous high-precision, low-power, time-domain bulk-tuned offset cancellation technique for high-speed dynamic comparator. The proposed offset cancellation technique minimizes the offset by using bulk-tuning in conjunction with offset sampling in the time domain. The proposed phase detector eliminates the dead zone and is symmetric to both outputs. An energy and area-efficient charge pump with offset polarity-based selectivity is also introduced. The proposed offset cancellation scheme is implemented in 65-nm CMOS technology with a 1.2 V supply, and analytical modeling of the time difference of comparator outputs and offset is also presented. The proposed design has a power consumption of 65.8 μW and maintains a calibration speed of 1 GHz with the comparator operating at 2 GHz frequency. The standard deviation of the offset is decreased to 33.3 μV from 2.183 mV, qualifying it for high-speed, high-precision applications.

Abstract: Neural amplifiers are desired to have ultra low power, low noise, low area, high input impedance, band pass response and high CMRR. Capacitively coupled instrumentation amplifier (CCIA) is a widely used topology as it features high power efficiency and moderate area, CMRR and input impedance. The main idea of area minimization relies on the minimum value implementation of the feedback capacitor of the CCIA and optimum mid band gain.We have proposed a feedback network which gives better mismatch for a given equivalent feedback capacitor which allows us to minimize the feedback capacitance without degrading the CMRR and gain mismatch. The amplifier implemented in 180 nm CMOS technology has among the lowest reported area of 0.006 mm2 and has an input capacitance of 1 pF. The amplifier consumes 1.08 μW of power and has an NEF of 5.2 with input referred noise of 12.4 μV in 1 - 5 KHz bandwidth. The post layout simulation results of the amplifier are presented.

This paper proposes a calibration technique agnostic calibration logic circuitry for the self-calibration of the high-precision dynamic comparator, which can be used in major self-calibration techniques to activate the calibration and offset polarity change detection for completion of the calibration. This paper also briefly reviews the different comparator offset cancellation techniques, i.e., auto-zeroing, self-calibration, and chopper stabilization. The proposed calibration logic is implemented in a dynamic comparator's effective trans-conductance controlled offset calibration in SCL 180 nm technology. The standard deviation of the input-referred offset of the comparator is reduced to 445 μV from 2.85 mV with a complete calibration range of 5σ offset, therefore qualifying it for high-speed flash ADCs and asynchronous SAR ADCs. The power consumption at 1 GHz operating frequency is 154.6 μW.

This paper presents a low-power 6-bit 1 GS/s partially active flash analog-to-digital converters (ADC) in 65-nm CMOS technology. A novel comparator offset correction technique is proposed, which does not require additional foreground calibration cycles. The partially active second-stage comparison is employed for power efficiency. A third-stage comparison is introduced for offset correction using fifteen low-offset comparators, out of which two are activated. The 0.5-bit redundancy from the first-stage provides the tolerance to track-and-hold (T/H) buffer settling error for high-speed applications. The simulation results show that the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 36.36 dB and a spurious-free dynamic range (SFDR) of 48.65 dB at a Nyquist frequency of 500 MHz with the power consumption of 13.98 mW.