Post Doctoral Researcher, System on Chip (SoC) Center
National Chung Cheng University, Taiwan
I am a Post-Doc Researcher in SoC center, Electrical Engineering at the National Chung Cheng University, Taiwan under the mentorship of Distinguished Prof. J. S. Wang. I have completed my PhD in July 2025 from Indian Institute of Technology Ropar, India under the guidance of Dr. Devarshi Mrinal Das and Dr. Vinayak Hande. I earned my B.E. with Honors in Electronics and Communication from Chandigarh College of Engineering and Technology, Punjab University, Chandigarh, India, in 2019.
I am a researcher in Integrated Circuit design with specialization in analog and mixed-signal domains. My PhD focused on high-speed, low-power dynamic comparator design and offset calibration for advanced ADC applications, while my current work extends into digital in-memory computing and low-voltage neural network accelerators for edge AI. I am passionate about developing energy-efficient neural network accelerator design for edge AI and cryogenic CMOS circuits, advancing scalable computing from ambient edge devices to quantum systems. With a strong record of publications, tape-outs, and interdisciplinary collaborations, I aim to advance next-generation semiconductor technologies through innovative research, impactful teaching, and industry-academic partnerships.
Beyond my academic pursuits, I enjoy gardening and immersing myself in nature.
Direct PhD, Indian Institute of Technology Ropar, Punjab, India (2019-2025)
B.E. in Electronics and Communication, Chandigarh College of Engineering and Technology, Punjab University, Chandigarh, India (2015-2019)
Accelerator Design
Cryogenic CMOS Circuit Design
Analog and Mixed Signal IC Design
Data Converters
CMOS circuit Design Automation
SRAM Based IMC Design
General Electronics (UG. Level)
Circuit Simulation Lab (PG. Level)
Mixed Signal IC design (PG. Level)
Analog IC design (PG. Level)
Active Filter Design (PG. Level)