Contributions

Journal Papers

• 1. A. K. Amaram, S. Kharwar, and T. K. Agarwal. "Investigation of resistive switching in Au/MoS2/Au using Reactive Molecular Dynamics and ab-initio quantum transport calculations." IEEE Electron Device Letters (2025). 

  2. J. Cao, G. Gandus, T. Agarwal, M. Luisier, and Y. Lee, "Dynamics of van der Waals charge qubit in two-dimensional bilayer materials: Ab initio quantum transport and qubit measurement," Physical Review Research 4, 043073, Oct. 2022.

  3. S. Papadopoulos, T. Agarwal, A. Jain, T. Taniguchi, K. Watanabe, M. Luisier, A. Emboras, and L. Novotny, "Ion Migration in Monolayer MoS2 Memristors", Physical Review Applied, vol. 18, no. 1, p.014018, July 2022. 

  4.  T. Agarwal, Y. Lee, and M. Luisier, "Circuit-aware Device Modeling of Energy-efficient Monolayer WS2 Trench-FinFETs." arXiv preprint arXiv:2104.07891, Apr. 2021. 

  5.  A. Gaur, T. Agarwal, I. Asselberghs, I. Radu, M. Heyns, and D. Lin, "A MOS capacitor model for ultra-thin 2D semiconductors: the impact of interface defects and channel resistance," 2D Materials, vol. 7, no. 3, p.035018, May 2020. 

  6.  T. Agarwal, M. Rau, I. Radu, M. Luisier, W. Dehaene and M. Heyns, ''Performance Comparison of s-Si, In0.53Ga0.47As, Monolayer BP- and WS2-Based n-MOSFETs for Future Technology Nodes-Part II: Circuit-Level Comparison," IEEE Transactions on Electron Devices, vol. 66, no. 8, pp. 3614-3619, Aug. 2019.

  7.  T. Agarwal, M. Rau, I. Radu, M. Luisier, W. Dehaene and M. Heyns, ''Performance Comparison of s-Si, In0.53Ga0.47As, Monolayer BP- and WS2-Based n-MOSFETs for Future Technology Nodes--Part I: Device-Level Comparison," IEEE Transactions on Electron Devices, vol. 66, no. 8, pp. 3608-3613, Aug. 2019.

  8.  T. Agarwal, G. Fiori, B. Sorée, I. Radu, M. Heyns and W. Dehaene, ''Material-Device-Circuit Co-design of 2D Materials based Lateral Tunnel FETs," IEEE Journal of the Electron Devices Society, vol. 6, pp. 979-986, Apr. 2018.

  9.  Y. Balaji, Q. Smets, C.J.L. de la Rosa, A.K.A. Lu, D. Chiappe, T. Agarwal, D. Lin, C. Huyghebaert, I. Radu, D. Mocuta, and G. Groeseneken, ''Tunneling Transistors based on MoS2/MoTe2 Van der Waals Heterostructures," IEEE Journal of the Electron Devices Society, vol. 6, pp. 1048 - 1055, Mar. 2018.

  10.  T. Agarwal, B. Sorée, I. Radu, P. Raghavan, G. Iannaccone, G. Fiori, W. Dehaene and M. Heyns,, ''Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes," Scientific Reports, vol. 7, no. 5016, pp. 1-7, Jul. 2017.

  11.  G. V. Resta, T. Agarwal, D. Lin, I. P. Radu, F. Catthoor, P. E. Gaillardon and G. De Micheli, ''Scaling trends and performance evaluation of 2-dimensional polarity-controllable FETs," Scientific Reports, vol. 7,no. 45556, pp. 1-9, Mar. 2017.

  12.  T. Agarwal, B. Sorée, I. Radu, P. Raghavan, G. Fiori, G. Iannaccone, A. Thean, M. Heyns and W. Dehaene, ''Comparison of short-channel effects in monolayer MoS2 based junctionless and inversion-mode field-effect transistors," Applied Physics Letters, vol. 108, no. 2, pp. 023506, Jan. 2016.

  13.  A. K. A. Lu, G. Pourtois, T. Agarwal, A. Afzalian, I. P. Radu and M. Houssa, ''Origin of the performances degradation of two-dimensional-based metal-oxide-semiconductor field effect transistors in the sub-10 nm regime: A first-principles study," Applied Physics Letters, vol. 108, no. 4, pp. 043504, Jan. 2016.

  14.  T. Agarwal, D. Yakimets, P. Raghavan, I. Radu, A. Thean, M. Heyns and W. Dehaene, ''Benchmarking of MoS2 FETs with Multigate Si-FET Options for 5 nm and Beyond," IEEE Transactions on Electron Devices, vol. 62, no. 12, pp. 4051-4056, Dec. 2015.

  15.  T. Agarwal, A. Nourbakhsh, P. Raghavan, I. Radu, S. De Gendt, M. Heyns, M. Verhelst and A. Thean, ''Bilayer Graphene Tunneling FET for Sub-0.2 V Digital CMOS Logic Applications," IEEE Electron Device Letters, vol. 35, no. 12, pp. 1308-1310, Dec. 2014.

  16.  A. Nourbakhsh, T. Agarwal, A. Klekachev, I. Asselberghs, M. Cantoro, C. Huyghebaert, M. Heyns, M. Verhelst, A. Thean and S. De Gendt, ''Chemically enhanced double-gate bilayer graphene field-effect transistor with neutral channel for logic applications," Nanotechnology, vol. 25, no. 34, pp. 345203, Aug. 2014.

  17.  T. Agarwal and M. J. Kumar, ''A dc model for partially depleted SOI laterally diffused MOSFETs utilizing the HiSIM-HV compact model," Journal of Computational Electronics, vol. 12, no. 3, pp. 460-468, May 2013.

  18.  T. Agarwal, A. R. Trivedi, V. Subramanian and M. J. Kumar, ''Compact Modeling of Partially Depleted Silicon-on-Insulator Drain-Extended MOSFET (DEMOSFET) Including High-Voltage and Floating-Body Effects," IEEE Transactions on Electron Devices, vol. 58, no. 10, pp. 3485-3493, Oct. 2011.

Conference Presentations

• 1. M. Tewari, A. K. Amaram, and T. K. Agarwal, "Multi-physics Modeling of Au/MoS2/Au Memristors combining Molecular Dynamics and Electro-thermal Simulations, " In 2025 9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Mar. 2025. 

  2. S. Kharwar, S. Sinha, and T. K. Agarwal, "Ohmic Au-MoS2 Contacts Enabled by Re Adsorbed MoS2 Source/Drain Regions: An Ab-initio Quantum Transport Study." In 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), pp. 1-3. Mar. 2024. 

  3. O. Maheshwari, J. Cao, Y. Lee, M. Luisier, and T. Agarwal, "Radio Frequency Performance of High Mobility 2D Monolayer Au2S-based Transistors," In 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), pp. 1-3. Mar. 2023. 

  4. G. Gandus, J. Cao, T. K. Agarwal, M. Luisier, and Y. Lee, "Ab initio quantum transport simulations of defective devices based on 2-D materials via a projected-GW approach," IEEE International Electron Devices Meeting (IEDM), Dec. 2022.

  5. Y. Lee, T. Agarwal and M. Luisier, "Ab initio modeling framework for Majorana transport in 2D materials: towards topological quantum computing," IEEE International Electron Devices Meeting (IEDM), pp. 30.3.1-30.3.4, Dec. 2020 (Virtual mode).

  6.  T. Agarwal, Á. Szabó, M.G. Bardon, B. Sorée, I. Radu, P. Raghavan, M. Luisier, W. Dehaene and M. Heyns, ''Benchmarking of monolithic 3D integrated MX2 FETs with Si FinFETs," IEEE International Electron Devices Meeting (IEDM), pp. 5-7, San Francisco, CA, USA, Dec. 2017.

  7.  T. Agarwal, B. Sorée, I. Radu, P. Raghavan, G. Fiori, M. Heyns and W. Dehaene, ''Material selection and device design guidelines for two-dimensional materials based TFETs," European Solid-State Device Research Conference (ESSDERC), pp. 54-57, Leuven, Belgium, Sept. 2017.

  8.  T. Agarwal, I. Radu, P. Raghavan, G. Fiori, A. Thean, M. Heyns and W. Dehaene, ''Effect of material parameters on two-dimensional materials based TFETs: An energy-delay perspective," European Solid-State Device Research Conference (ESSDERC), pp. 47-50, Lausanne, Switzerland, Sept. 2016.

  9.  T. K. Agarwal, O. Badami, S. Ganguly, S. Mahapatra and D. Saha, ''Design optimization of gate-all-around vertical nanowire transistors for future memory applications," IEEE International Conference of Electron Devices and Solid-state Circuits, pp. 1-2, Hong Kong, China, Jun. 2013.

  10.  T. K. Agarwal and M. J. Kumar, ''Modeling of Partially Depleted SOI DEMOSFETs with a Sub-circuit Utilizing the HiSIM-HV Compact Model," International Conference on VLSI Design, pp. 406-411, Bangalore, India, Jan. 2012.

  11.  T. Agarwal, A. Sawhney, A. K. Kureshi and Mohd. Hasan, ''Performance Comparison of CNFET and CMOS Based Full Adders at the 32nm Technology Node," Proceedings of VLSI Design and Test Symposium (VDAT), pp. 49-57, Bangalore, India, Jul. 2008.

  12.  T. K. Agarwal, A. Sawhney, A. K. Kureshi and Mohd. Hasan, ''Performance comparison of static CMOS and MCML gates in sub-threshold region of operation for 32nm CMOS technology," International Conference on Computer and Communication Engineering, pp. 284-287, Kuala Lumpur, Malaysia, May 2008.

Patents

• 1. A. Nourbakhsh, B. Soree, M. Heyns, T. K. Agarwal, ''Bilayer graphene tunneling field effect transistor," US9293536, Mar. 2016 (Issued).