Windows application to collect data from serial port, display on screen, and save to hard drive
Main FPGA Verilog file (for Vivado 2018.2)
C source file for SDK (for Vivado 2018.2)
Verilog file to enable 4-digit hex display - HexDisplayV2.v at UMN MXP
Serial UART Receive Module from Nandland.com (uart_rx.v)