Device/Process Simulator Development
Boltzmann Transport
Approach: Full-Band/Effecitve Mass Semi-Classical Monte Carlo Carrier Transport
Target: Si/Ge/SiGe/III-V/2D Material Planar/Fin/GAA FET
Related Publications
- D. H. Lee, S. Youn, Y. Ha, J. Chang*, “Full-Band Semi-Classical Monte Carlo Simulation of Layer Number-Dependent Hole Transport in W- and Mo-Based Transition Metal Dichalcogenides”, SISPAD, Sep 28-30, 2026, Kumamoto, Japan.
- S. Kang, Y. Ha, I. Yun, J. Chang*, “Strain-Dependent Electron Transport in Mono-, Bi-, and Trilayer MoS2 and WS2 Using Coupled First-Principles and Full-Band Semi-Classical Monte Carlo Simulation”, SISPAD, Sep 28-30, 2026, Kumamoto, Japan.
- U. Lee, J. Kim, J. Chang*, “Semi-Classical Monte Carlo Simulation of Contact Geometry Effect on Source/Drain Junction Resistance in N-Type Si Fin and Nanosheet FETs”, SISPAD, Sep 28-30, 2026, Kumamoto, Japan.
- D. H. Lee, S. W. Kang, L. F. Register, S. K. Banerjee, J. Chang*, “Efficient and Accurate Full Band Semi-Classical Monte-Carlo Transport Simulation Using Smearing Method and Marching Tetrahedra Algorithm”, SISPAD, Sep 24-26, 2025, Grenoble, France.
- S. Youn, D. H. Lee, J. Chang*, “Full Band Semi-Classical Monte-Carlo Simulation of Layer Number-Dependent Electron Transport in MoS2 and InSe”, SISPAD, Sep 24-26, 2025, Grenoble, France.
- U. Lee, J. Kim, B. H. Hong, W. Kwon, B. T. Archer, L. F. Register, S. K. Banerjee, J. Chang*, “Semi-Classical Monte Carlo Simulation of Quantum Confinement Effects in Si Nanosheet and Fin FETs in Industry Standard Orientation”, IEEE Electron Device Letters, vol. 47, no. 2, pp. 225-228 (2026). [Link]
Quantum Transport
Approach: Non-Equilibrium Green's Function, Quantum Transmitting Boundary Method
Target: 2D Material Planar/GAA/Tunneling FET, Topological Semimetal Interconnect
Related Publications
- S. Youn, H. J. Han, J. Chang*, “Thickness-Dependent Conductivity Scaling of B20-Type Chiral Topological Semimetals for Beyond-Cu Interconnect Applications”, SISPAD, Sep 28-30, 2026, Kumamoto, Japan.
- E. Yang, K. R. Kim, J. Chang*, “Theoretical Evaluation of Two-Dimensional Ferroelectric Material CuInP2S6 for Ferroelectric Tunnel Junction Device”, IEEE Electron Device Letters, vol. 42, no. 10, pp. 1472-1475 (2021). [Link]
TCAD Process Simulator
Approach: Level-Set
Target: Topology (Etching, Deposition), Implant, Diffusion
Material Modeling
FEOL
Approach: Density Functional Theory, Quantum Transport, Molecular-Dynamic Simulation
Target: Gate Stack, Silicide Contact, Memory Device (Resistive RAM, Selector Only Memory)
Related Publications
- C. Lim, J. Chang*, “Theoretical Benchmarking of Ni/Co/Ti/Mo-Silicide Contact Resistance on N-Type Doped Silicon”, IEEE Transactions on Electron Devices, vol. 73, no. 4, pp.2299-2307 (2026). [Link]
- J. H. Song=, C. Lim=, J.-S. Jeong=, S. Park, M. K. Yang*, J. Chang*, G. H. Kim*, “Carbon-doped GeTe-based ovonic threshold switch for highly reliable artificial neuron devices”, International Journal of Extreme Manufacturing, 8, 035502 (2026). [Link]
BEOL
Approach: Density Funcdtional Theory, Boltzmann Transport, Quantum Transport
Target: Interconnect Metal (Conductivity, Grain Boundary Resistance, Reliability), Low-k Dielectric, Via
Related Publications
- S. Youn, H. J. Han, J. Chang*, “Thickness-Dependent Conductivity Scaling of B20-Type Chiral Topological Semimetals for Beyond-Cu Interconnect Applications”, SISPAD, Sep 28-30, 2026, Kumamoto, Japan.
- S. W. Kang, S. Park, J. Chang*, “Theoretical Screening of Co- and Mo-Based Binary Alloys for Interconnect Metal”, Journal of Materials Chemistry C , 14, 6251-6256 (2026). [Link]
- S. Park, S. W. Kang, G. Kim, J. Moon, K. Lee*, J. Chang*, “Theoretical Evaluation of Reliability and Via Resistance of Liner-less Co Interconnect Using Co-Ti Binary Alloy”, IEEE Transactions on Electron Devices, vol. 72, no. 10, pp. 5703-5709 (2025). [Link]
TCAD
Advanced Technology Node
Approach: TCAD Device/Process Simulation
Target: Nanosheet/Forksheet/Complementary FET
Related Publications
- M. Lim, J. Chang*, “Si CMOS-Compatible Ternary Logic Technology Enabled by On-Current Limiting Resistance”, IEEE Electron Device Letters, vol. 47, no. 1, pp. 21-24 (2026). [Link]
Experiment
2D Material/Si/Oxide FET
Related Publications
- C. Lee=, D. Kim=, E. Yang, J. Ma, K. Kang*, J. Chang*, “Electrically Binary and Ternary Convertible CMOS Inverter and Logic Gate Using Complementary Field-Effect Transistors Based on Vertically Stacked MoS2/WSe2 n-/p- Field-Effect Transistors”, Advanced Functional Materials, 36, e10164 (2026). [Link]
- J. Ma, E. Yang, C. Lee, J. Seok, J. Chang*, “Large-Scale Implementation of Vertical Sidewall and Vertical Multi-Channel WS2 Nanosheet Field-Effect Transistors for Area-Efficient Integrated Circuit”, Small, 21, 42, e08533 (2025). [Link]
- J. Seok, J. E. Seo, D. K. Lee, J. Y. Kwak*, J. Chang*, “Attoampere Level Leakage Current in Chemical Vapor Deposition-Grown Monolayer MoS2 Dynamic Random-Access Memory in Trap-Assisted Tunneling Limit”, ACS Nano, 19, 2, 2458–2467 (2025). [Link]
- E. Yang=, S. Hong=, J. Ma=, S.-J. Park, D. K. Lee, T. Das, T.-J. Ha*, J. Y. Kwak*, J. Chang*, “Realization of Extremely High-Gain and Low-Power in nMOS Inverter Based on Monolayer WS2 Transistor Operating in Subthreshold Regime”, ACS Nano, 18, 34, 22965–22977 (2024). [Link]
- J. E. Seo=, M. Gyeon=, J. Seok, S. Youn, T. Das, S. Kwon, T. S. Kim, D. K. Lee, J. Y. Kwak*, K. Kang*, J. Chang*, “Improvement of Contact Resistance and Three-Dimensional Integration of Two-Dimensional Material Field-Effect Transistors Using Semi-metallic PtSe2 Contacts”, Advanced Functional Materials, 34, 2407382 (2024). [Link] 'Top 10% of Most-Viewed Papers Published by Advanced Functional Materials in 2024'