Publications

Bold Our Group Member, * Corresponding Author, = Equal Contribution

• 1. S. W. Kang, S. Park, J. Chang*, “Theoretical Screening of Co- and Mo-Based Binary Alloys for Interconnect Metal”, submitted.

  2.  D. H. Lee, S. W. Kang, L. F. Register, S. K. Banerjee,  J. Chang*, “Improved Accuracy and Efficiency in Full-Band Semi-Classical Monte Carlo Carrier Transport Simulations via Smearing and Marching Tetrahedra Methods", submitted.

  3. C. Lee, J. Seok, J. Chang*, “Impact of Self-Heating Induced Performance Degradation on Leakage Current Estimation in Capacitorless Dynamic Random Access Memory Based on Monolayer MoS2", submitted.

  4. E. Yang, J. Ma, C. Lee, J. Chang*, “1T XNOR and Program Gate-Less Reconfigurable Logic Operation Using Dual n-/p-Channel Ambipolar WSe2 Field-Effect Transistors with Charge-Trapping Layer”, submitted.

  5. C. Lim=, S. Park=, J. Chang*, “First-Principle Calculations of Interfacial Resistance between Nickel Silicide and Hyperdoped Silicon with N-Type Dopants Arsenic, Phosphorus, Antimony, Selenium and Tellurium”, submitted.

  6. J. Ma, E. Yang, C. Lee, J. Seok, J. Chang*, “Large-Scale Implementation of Vertical Sidewall and Vertical Multi-Channel WS2 Nanosheet Field-Effect Transistors for Area-Efficient Integrated Circuit”, is accepted for publication in Small.

  7. S. Park, S. W. Kang, G. Kim, J. Moon, G K. Lee*, J. Chang*, “Theoretical Evaluation of Reliability and Via Resistance of Liner-less Co Interconnect Using Co-Ti Binary Alloy”, is accepted for publication in IEEE Transactions on Electron Devices.

  8. E.-H. Kim=, C. Lee=,  S.-R. Park, J. Chang*, T.-J. Ha*, “Restorative Effects of Low-Temperature Post-Sulfur Annealing on Device Performance of Monolayer MoS2 Transistors for NMOS Inverters”, is accepted for publication in Small. [Link]

  9. C. Lee=, D. Kim=, E. Yang, J. Ma, K. Kang*, J. Chang*, “Electrically Binary and Ternary Convertible CMOS Inverter and Logic Gate Using Complementary Field-Effect Transistors Based on Vertically Stacked MoS2/WSe2 n-/p- Field-Effect Transistors”, is accepted for publication in Advanced Functional Materials. [Link]

  10. J. Kim=, B. Kim=, J. Ma=, S.-Y. Lim, M.-H. Choi, H. Jeong, J. Ji, J.-H. Kang, J. Chang*, J. Kwon*, T. J. Park*, “Energy-Efficient, Scalable Single-Layer MoS2−Based Synaptic Field-EffectTransistors”, ACS Applied Electronic Materials, 7, 14, 6491–6498 (2025). [Link]

  11. D. H. Lee, S. R. Das, J. Kwon*,  J. Chang*, “FDSOI-Based Reconfigurable FETs: A Ferroelectric Approach”, IEEE Transactions on Nanotechnology,  vol. 24, pp. 277-281 (2025). [Link]

  12. J. Seok, J. E. Seo, D. K. Lee, J. Y. Kwak*, J. Chang*, “Attoampere Level Leakage Current in Chemical Vapor Deposition-Grown Monolayer MoS2 Dynamic Random-Access Memory in Trap-Assisted Tunneling Limit”, ACS Nano, 19, 2, 2458–2467 (2025). [Link]

  13. S. H. Kim, J. Seo, J. Koo, J. Chang*, Gangtae Jin* and H. J. Han*, “Topological Semimetals for Advanced Node Interconnects”, iScience, 27, 12, 111460 (2024). [Link]

  14. M. Gyeon=, J. E. Seo=, S. Oh, G. Noh, C. Lee, M. Choi, S. Kwon, T. S. Kim, H. Y. Jeong, S. Song*, J. Chang*, K. Kang*, “Wafer-Scale Growth of Ultra-Uniform 2D PtSe2 Films with Spatial and Thickness Control Through Multi-Step Metal Conversion”, ACS Nano, 18, 50, 33977–33987 (2024). [Link]

  15. E. Yang=,  S. Hong=, J. Ma=,  S.-J. Park, D. K. Lee, T. Das, T.-J. Ha*, J. Y. Kwak*, J. Chang*, “Realization of Extremely High-Gain and Low-Power in nMOS Inverter Based on Monolayer WS2 Transistor Operating in Subthreshold Regime”,  ACS Nano, 18, 34, 22965–22977 (2024). [Link]

  16. J. E. Seo=, M. Gyeon=, J. Seok, S. Youn, T. Das, S. Kwon, T. S. Kim, D. K. Lee, J. Y. Kwak*, K. Kang*, J. Chang*, “Improvement of Contact Resistance and Three-Dimensional Integration of Two-Dimensional Material Field-Effect Transistors Using Semi-metallic PtSe2 Contacts”, Advanced Functional Materials, 2407382 (2024). [Link]

  17. D. G. Jeong=, E. Park=, Y. Jo=, E. Yang=, G. Noh, D. K. Lee, M. J. Kim, Y. J. Jeong, H. J. Jang, D. J. Joe, J. Chang*, J. Y. Kwak*, “Grain Boundary Control for High-Reliability HfO2-based RRAM”, Chaos, Solitons and Fractals, 183, 114956 (2024). [Link]

  18. T. Das, S. Youn, J. E. Seo, E. Yang, J. Chang*, “Large-Scale Complementary Logic Circuit Enabled by Al2O3 Passivation-Induced Carrier Polarity Modulation in Tungsten Diselenide”, ACS Applied Materials & Interfaces, 15, 45116−45127 (2023). [Link]

  19. S. Youn, J. Chang*, “Computational Analysis of Metal Contact on Bi2O2Se with Se Surface Vacancies”, Advanced Electronic Materials, 9, 2201221 (2023). [Link]

  20. E. Park=, J. E. Seo=, G. Noh, Y. Jo, I. S. Kim, J. Park, J. Kim, Y. Jeong, S. Lee, I. Kim, J.-K. Park, S. Kim, J. Chang*, J. Y. Kwak*, “Pentagonal 2D Layered PdSe2-based Synaptic Device with Graphene Floating Gate”, Journal of Materials Chemistry C, 10, 16536–16545 (2022). [Link]

  21. J. E. Seo, E. Park, J. Y. Kwak*, J. Chang*, “Demonstration of PdSe2 CMOS Using Same Metal Contact in PdSe2 n-/p-MOSFETs through Thickness-Dependent Phase Transition”, Advanced Electronic Materials, 8, 2200485 (2022). [Link]

  22. C. H. Lee, Y. Park, S. Youn, M. J. Yeom, H. S. Kum, J. Chang, J. Heo*, G. Yoo*, “Design of p-WSe2/n-Ge Heterojunctions for High-Speed Broadband Photodetectors”, Advanced Functional Materials, 32, 2107992 (2022). [Link]

  23. A. Hwang, M. Park, Y. Park, Y. Shim, S. Youn, C. H. Lee, H. B. Jeong, H. Y. Jeong, J. Chang, K. Lee*, G. Yoo*, J. Heo*, “Visible and infrared dual-band imaging via Ge/MoS2 van der Waals heterostructure”, Science Advances, 7 (2021). [Link]

  24. J. E. Seo, T. Das, E. Park, D. Seo, J. Y. Kwak*, J. Chang*, “Polarity Control and Weak Fermi-Level Pinning in PdSe2 Transistor”, ACS Applied Materials & Interfaces, 13, 43480-43488 (2021). [Link]

  25. E. Yang, K. R. Kim, J. Chang*, “Theoretical Evaluation of Two-Dimensional Ferroelectric Material CuInP2S6 for Ferroelectric Tunnel Junction Device”, IEEE Electron Device Letters, vol. 42, no. 10, pp. 1472-1475 (2021). [Link]

  26. V. A. Cao, M. Kim, W. Hu, S. Lee, S. Youn, J. Chang, H. S. Chang, J. Nah*, "Enhanced Piezoelectric Output Performance of the SnS2/SnS Heterostructure Thin-Film Piezoelectric Nanogenerator Realized by Atomic Layer Deposition", ACS Nano, 15, 10428-10436 (2021). [Link]

  27. D. Seo=, J. E. Seo=, T. Das, J. Y. Kwak*, J. Chang*, “Gate-Controlled  Rectifying Direction in PdSe2 Lateral Heterojunction Diode”, Advanced Electronic Materials, 7, 2100005 (2021). [Link]

  28. T. Das, E. Yang, J. E. Seo, J. H. Kim, E. Park, M. Kim, D. Seo, J. Y. Kwak*, J. Chang*, “Doping-Free All PtSe2 Transistor via Thickness-Modulated Phase Transition”, ACS Applied Materials & Interfaces, 13, 1861-1871 (2021). [Link]

  29. E. Park, M. Kim, T. S. Kim, I. S. Kim, J. Park, J. Kim, Y. Jeong, S. Lee, I. Kim, J. Park, G. T. Kim, J. Chang*, K. Kang*, J. Y. Kwak*, “A 2D Material-based Floating Gate Device with Linear Synaptic Weight Update”, Nanoscale 12, 24503-24509 (2020). [Link]

  30. S. Kim, J. Y. Park, J. Chang*, K. R. Kim*, “Scaling and Variation Predictions for Silicon Fin-Based High Electron Mobility Transistor”, IEEE Electron Device Letters, vol. 41, no. 11, pp. 1621-1624 (2020). [Link]

  31. E. Yang, J. E. Seo, D. Seo, J. Chang*, “Intrinsic limit of contact resistance in the lateral heterostructure of metallic and semiconducting PtSe2”, Nanoscale 12, 14636-14641 (2020). [Link]

  32. T. Das, D. Seo, J. E. Seo, J. Chang*, “Tunable Current Transport in PdSe2 Via Layer-by-Layer Thickness Modulation by Mild Plasma”, Advanced Electronic Materials, 6, 2000008 (2020). [Link]

  33.  J. E. Seo, D. Seo, J. Chang*, “Theoretical Analysis on Ballistic Current Transport in Monolayer Black Arsenic MOSFETs”, IEEE Transactions on Electron Devices, vol. 67, no. 2, pp. 622-626 (2020). [Link]

  34. J. W. Jeong, Y. E. Choi, W. S. Kim, J. H. Park, S. Kim, S. Shin, K. J. Lee, J. Chang, S. J. Kim, and K. R. Kim*, “Tunneling-based ternary metal-oxide-semiconductor technology”, Nature Electronics 2, 307–312 (2019). [Link]

  35. D. Seo, J. Chang*, “Doping-Free Arsenene Heterostructure Metal-Oxide-Semiconductor Field Effect Transistors Enabled by Thickness Modulated Semiconductor to Metal Transition in Arsenene”, Scientific Reports 9, 3988 (2019). [Link]

  36.  J. Chang*, “Novel Antimonene Tunneling Field-Effect Transistors Using Abrupt Transition of Semiconductor to Metal in Monolayer and Multilayer Antimonene Heterostructure”, Nanoscale 10, 13652 (2018). [Link]

  37. P. Sarangapani*, C. Weber, J. Chang, S. Cea, M. Povolotskyi, G. Klimeck, T. Kubis, “Atomistic tight-binding study of contact resistivity in Si/SiGe PMOS Schottky contacts”, IEEE Transactions on Nanotechnology, vol. 17, no. 5, pp. 968-973 (2018). [Link]

  38. A. Valsaraj*, J. Chang, A. Rai, L. F. Register, E. Tutuc, S. K. Banerjee, “Theoretical and experimental investigation of vacancy-based doping of monolayer MoS2 on oxide”, 2D Materials 2 (4), 045009 (2015). [Link]

  39. A. Rai*, A. Valsaraj, H. CP Movva, A. Roy, R. Ghosh, S. Sonde, S. Kang, J. Chang, T. Trivedi, R. Dey, S. Guchhait, S. Larentis, L. F. Register, E. Tutuc, S. K. Banerjee, “Air Stable Doping and Intrinsic Mobility Enhancement in Monolayer Molybdenum Disulfide by Amorphous Titanium Suboxide Encapsulation”, Nano Letters 15 (7), 4329 (2015). [Link]

  40. J. Chang*, “Modeling of anisotropic two-dimensional materials monolayer HfS2 and phosphorene metal-oxide semiconductor field effect transistors“, Journal of Applied Physics 117, 214502 (2015). [Link]

  41. J. Chang*, “Simulation of channel orientation dependent transport in ultra-scaled monolayer MoX2 (X = S, Se, Te) n-MOSFETs“, Journal of Physics D: Applied Physics  48, 145101 (2015). [Link]

  42. J. Chang*, C. Hobbs, “Theoretical Study of Phosphorene Tunneling Field Effect Transistors”, Applied Physics Letters 106, 083509 (2015). [Link]

  43. J. Chang*, S. Larentis, E. Tutuc, L.F. Register, S. K. Banerjee, “Atomistic Simulation of the Electronic States of Adatoms in Monolayer MoS2”, Applied Physics Letters 104, 141603 (2014). [Link]

  44. J. Chang*, L.F. Register, S. K. Banerjee, “Ballistic Performance Comparison of Monolayer Transition Metal Dichalcogenide MX2 (M = Mo, W; X = S, Se, Te) MOSFETs”, Journal of Applied Physics 115, 084506 (2014). [Link]

  45. J. Chang*, L.F. Register, S. K. Banerjee, “Atomistic Full-Band Simulations of Monolayer MoS2 Transistor”, Applied Physics Letters 103, 223509 (2013). [Link]

  46. J. Chang*, L.F. Register, S. K. Banerjee, “Topological Insulator Bi2Se3 Thin Films as an Alternative Channel Material in MOSFETs”, Journal of Applied Physics 112, 124511 (2012). [Link]

  47. J. Chang, P. Jadaun, L.F. Register, S. K. Banerjee, B. Sahu*, “Dielectric Capping Effects on Binary and Ternary Topological Insulator Surface States”, Physical Review B 84.155105 (2011). [Link]

  48. J. Chang, L. F. Register, S. K. Banerjee, B. Sahu*, “Density Functional Study of Ternary Topological Insulator Thin Films”, Physical Review B 83, 235108 (2011). [Link]

  49. J. Chang*, A. Kapoor, L. F. Register, S. K. Banerjee, “Analytical Models of Short-Channel Double Gate JFETs”, IEEE Transactions on Electron Devices, vol. 57, no. 8, pp. 1846-1855 (2010). [Link]

Bold Our Group Member, * Corresponding Author

• 1. D. H. Lee, S. W. Kang, L. F. Register, S. K. Banerjee, J. Chang*, “Efficient and Accurate Full Band Semi-Classical Monte-Carlo Transport Simulation Using Smearing Method and Marching Tetrahedra Algorithm”, SISPAD, Sep 24-26, 2025, Grenoble, France.

  2. S. Youn, D. H. Lee, J. Chang*, “Full Band Semi-Classical Monte-Carlo Simulation of Layer Number-Dependent Electron Transport in MoS2 and InSe”, SISPAD, Sep 24-26, 2025, Grenoble, France.

  3. U. Lee, J. Y. Kim, J. Chang*, “Semi-Classical Monte-Carlo Simulation of Quantum Confinement Effects in Si Fin and Nanosheet with Different Surface Orientations”, AWAD, Jul 3-4, 2025, Nara, Japan.

  4. J. Y. Kim, U. Lee, J. Chang*, “Semi-Classical Monte-Carlo Study of Contact Geometry Effect on Source/Drain Junction Resistance in Si Nanosheet FETs”, AWAD, Jul 3-4, 2025, Nara, Japan.

  5. C. Lim, S. Park, J. Chang*, “Machine-Learned Force Fields for Accurate and Efficient Atomistic Simulation of Carbon-Doped GeTe-Based Memory Device”, AWAD, Jul 3-4, 2025, Nara, Japan.

  6. E. Yang, J. Ma, C. Lee, J. Chang*, “Lage-Scale Reconfigurable Logic Gate using Ambipolar WSe2 Field-Effect Transistors with Charge-Trapping Layer ", DRC, Jun 22-25, 2025, Durham, NC, U.S.A.

  7. J. Ma, E. Yang, C. Lee, J. Chang*, “Large-Area Implementation of Monolayer WS2 Double-Gate Vertical Sidewall Field-Effect Transistors for Area-Efficient Integrated Circuit", DRC, Jun 22-25, 2025, Durham, NC, U.S.A.

  8. S. W. Kang, S. Park, J. Chang*, “Theoretical Evaluation of Co-Ti Binary Alloys in Terms of Reliability and Resistivity for Back-End of-Line Interconnect Application”, GCIM, Jun 15-19, 2025, Jeju, Korea.

  9. S. Park, J. Chang*, “Suppressing Resistivity Scaling in Interconnects with Topological Semimetals: A First-Principles and NEGF Study”, GCIM, Jun 15-19, 2025, Jeju, Korea.

  10. D. Seo, J. E. Seo, T. Das, J. Y. Kwak, J. Chang*, “Thickness-Dependent Transport in PdSe2 Field-Effect-Transistors”, AWAD, Jul 1-3, 2019, Busan, Korea.

  11. J. Chang*, “Tunneling Field-Effect Transistors Utilizing Thickness Modulated Semiconductor to Metal Transition in Two-Dimensional Materials”, AWAD, Jul 2-4, 2018, Kitakyushu, Japan.

  12.  P. Sarangapani*, C. Weber, J. Chang, S. Cea, R. Golizadeh-Mojarad, M. Povolotskyi, G. Klimeck, T. Kubis, “Assessment of Si/SiGe PMOS Schottky contacts through atomistic tight binding simulations: Can we achieve the 10−9 Ω.cm2 target ?”, IEEE-NANO, Jul 25-28, 2017, Pittsburgh, PA, U.S.A.

  13. A. Valsaraj*, J. Chang, L. F. Register, S. K. Banerjee, “Substitutional Doping of Metal Contact for Monolayer Transition Metal Dichalcogenides: a Density Functional Theory Based Study”, SISPAD, Sep 9-11, 2015, Washington DC, U.S.A.

  14. A. Valsaraj*, J. Chang, L. F. Register, S. K. Banerjee, “Density-Functional-Theory-Based study of monolayer MoS2 on Oxide”, SISPAD, Sep 9-11, 2014, Yokohama, Japan.

  15. A. Valsaraj,* J. Chang, L. F. Register, S. K. Banerjee, “DFT Study of the Effect of HfO2 on Monolayer MoS2”, ICPS, Aug 10-15, 2014, Austin, TX, U.S.A.

  16. A. Valsaraj*, J. Chang, L. F. Register, S. K. Banerjee, “Effect of HfO2 and Al2O3 on monolayer MoS2 electronic structure”, DRC, Jun 22-25 , 2014, Santa Barbara, CA, U.S.A.

  17. J. Chang*, L. F. Register, S. K. Banerjee, “Comparison of Ballistic Transport Characteristics of Monolayer Transition Metal Dichalcogenides (TMDs) MX2 (M =  Mo, W; X = S, Se, Te) n-MOSFETs”, SISPAD, Sep 3-5, 2013, Glasgow, Scotland, U.K.

  18. J. Chang*, L. F. Register, S. K. Banerjee, “Full-Band Quantum Transport Simulations of Monolayer MoS2 Transistors: Possibility of Negative Differential Resistance”, DRC, Jun 23-26 , 2013, Notre Dame, IN, U.S.A.

  19. J. Chang*, L. F. Register, S. K. Banerjee, “Computational Study of Tunnel FETs Based on Topological Insulator Bi2Se3”, Techcon 2012, Sep 10-11, 2012, Austin, TX. U.S.A. [Best in Session Paper Award]

  20. J. Chang*, L. F. Register, S. K. Banerjee, “Atomistic Quantum Transport Simulation of Topological Insulator Bi2Se3 Tunnel FETs”, SISPAD, Sep 5-7, 2012, Denver, CO, U.S.A.

  21. J. Chang*, L. F. Register, S. K. Banerjee, “Possible Applications of Topological Insulator for Tunnel FETs”, DRC, Jun 18-20 , 2012, University Park, PA, U.S.A.

  22. J. Chang*, L. F. Register, S. K. Banerjee, B. Sahu, “Thin Film Electronic Properties of Ternary Topological Insulator”, 2011 MRS Fall Meeting, Nov 28-Dec 2 , 2011, Boston, MA, U.S.A.

  23. J. Chang*, L. F. Register, S. K. Banerjee, B. Sahu, “Effect of Dielectric Materials on the Topological Insulator Bi2Se3 Surface States“, Techcon 2011, Sep 12-13, 2011, Austin, TX. U.S.A.

  24. B. Sahu*, J. Chang, P. Jadaun, L. F. Register, S. K. Banerjee, A. H. MacDonald, “Surface States of Three-Dimensional Topological Insulators: How Robust are They?“, 2011 MRS Spring Meeting, Apr 25-29, 2011, San Francisco, CA, U.S.A.

  25. J. Chang*, L. F. Register, S. K. Banerjee, B. Sahu, “Effect of Dielectric Materials on the Topological Insulator Bi2Se3 Surface States”, 2011 APS March Meeting, Mar 21-25 , 2011, Dallas, TX, U.S.A.