Embedded Files
Frequency Division Multiplexing
Frequency Division Multiplexing
In this project, we tried to demonstrate how frequency division multiplexing works. We developed a Matlab app that visualizes every step of the process.
Digital Filter Design for Noise Removal from Real-Life Angiogram Signals using MATLAB
Digital Filter Design for Noise Removal from Real-Life Angiogram Signals using MATLAB
In this project, I demonstrated the use of FIR filters in the field of angiogram signals.
Obstacle Determination Using 555 Timer, Ultrasonic Sensor, and Buzzer
Obstacle Determination Using 555 Timer, Ultrasonic Sensor, and Buzzer
This project was a hardware project. The circuit was built on a breadboard. A 555 timer was used to trigger the ultrasonic sensor at regular intervals to emit a sound wave. The sound wave was then reflected back by any obstacle in its path and the time taken for the wave to return was measured by the ultrasonic sensor. This time was then used to calculate the distance of the obstacle using the speed of sound. If the distance was less than a certain threshold, the buzzer was triggered to alert the user.
Load Flow Analysis using Gauss-Seidel Method in MATLAB
Load Flow Analysis using Gauss-Seidel Method in MATLAB
I tried to develop a matlab script that can automate the load flow analysis using the Gauss Seidal method
Performance Evaluation of 6T, 7T, and 8T SRAM at 90 nm Technology
Performance Evaluation of 6T, 7T, and 8T SRAM at 90 nm Technology
In this project, we designed and compared 6T,7T and 8T SRAM. The results are presented in form of an IEEE paper.
Design and Implementation of a Finite State Machine for Robotic Arm Control
Design and Implementation of a Finite State Machine for Robotic Arm Control
In this project we developed an FSM in Verilog HDL to control robotic arm operations (Idle, Pick, Place, Return) with deterministic state transitions. The design was implemented and verified in Cadence Virtuoso Genesis, including schematic, layout, DRC, and LVS checks. Ensured reliable, low-latency control through RTL-to-layout workflow, making it ASIC-ready.
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