Chip Gallery

Process: Commercial 28 nm CMOS

Application: Cryogenic IC Design

Publication: [IEEE TCAD'26] A Geometry-Scalable DC I–V Calibration Methodology for a Commercial Bulk CMOS Process Design Kit for Cryogenic ICs Operating Near 1 K

Significance:  Cryo-CMOS  This work provides an EDA-compatible, geometry-scalable methodology for calibrating a commercial CMOS PDK for cryogenic IC design. The improved DC I–V prediction accuracy near 1 K can accelerate the development of reliable cryogenic ICs for quantum-computing interfaces and other low-temperature systems. 

Process: Samsung 28 nm CMOS

Application: Wireline Interfaces

Publication: [IEEE TVLSI'26] A 3.2-GHz Ring-Oscillator-Based Charge-Pump PLL With Time-Domain Optimization of PFD Reset Delay

Significance:  Clocking  This work provides a SystemVerilog-based time-domain methodology for optimizing PFD reset delay in CP-PLLs by capturing CP current-waveform nonidealities that conventional phase-domain models miss. By accurately identifying the optimal PFD reset delay, the method can accelerate low-jitter, low-spur PLL design, as validated by a 28-nm 3.2-GHz prototype achieving 1.12-ps rms jitter and a −56.4-dBc reference spur. 

Process: Samsung 28 nm CMOS

Application: Die-to-Die Interfaces

Publication: [IEEE ESSERC'25] A 0.65-pJ/b, 11-Gb/s/pin Transmitter Employing Edge-Controlled Crosstalk Cancellation for Near-Complete Suppression of Crosstalk-Induced Jitter

Significance:  Wireline  This work presents an edge-controlled crosstalk cancellation TX that nearly eliminates crosstalk-induced jitter in densely coupled multi-channel links. By maintaining a 0.506-UI eye opening at 11 Gb/s/pin with adjacent aggressor channels, the proposed scheme can enable energy-efficient high-density I/O interfaces for advanced memory and chiplet systems. 

Process: Samsung 28 nm CMOS

Application: VLSI/Memory Modules

Publication: [IEEE TVLSI'25] A Compact Power-on-Reset Circuit With Configurable Brown-Out Detection 

Significance:  Power  This work presents a compact configurable POR/BOR circuit that provides reliable reset generation over a wide supply-ramp range while detecting brown-out events with programmable trip points. By integrating a voltage reference and an inverter-based trip point detector in a 995.3-μm² 28-nm prototype, the proposed circuit enables area-efficient supply monitoring for low-voltage CMOS systems. 

Process: UMC 28 nm CMOS

Application: Mobile Display Links

Publication: [IEEE TVLSI'25] A 10-Gb/s/lane, Energy-Efficient Transceiver With Reference-Less Hybrid CDR for Mobile Display Link Interfaces 

Significance:  Wireline  This work presents an energy-efficient embedded-clock display-link transceiver that reduces clock-distribution power and off-chip I/O channel count for mobile AP-to-TCON interfaces. By combining a latch-less serializer and a hybrid CDR with selective digital-loop deactivation, the 28-nm prototype achieves 10 Gb/s/lane operation with 1.23 pJ/b/lane, enabling low-power high-speed mobile display links. 

Process: Magna/Hynix 180 nm CMOS

Application: Multichannel Sensor Interfaces

Publication: [IEEE TVLSI'23] An Area/Power-Efficient ΔΣ Modulator Based on Dynamic-Boost Inverter for Multichannel Sensor Applications 

Significance:  Data Converter  This work demonstrates an area- and power-efficient DT ΔΣ modulator for multichannel sensor interfaces by combining compact self-biased dynamic-boost-inverter integrators with a quantitative GBW optimization strategy. The 0.18-μm CMOS prototype achieves an 84.0-dB peak SNDR and an 87.1-dB DR over a 25-kHz bandwidth in only 0.0939 mm², highlighting its suitability for compact, high-resolution sensor readout systems. 

Process: Samsung 28 nm CMOS

Application: IoT Sensor Interfaces

Publication: [IEEE TVLSI'22] A Fully-Passive Noise-Shaping SAR ADC Utilizing Last-Bit Majority Voting and Cyclic Dynamic Element Matching Techniques  

Significance:  Data Converter  This work presents a fully passive noise-shaping SAR ADC that supports DVFS-compatible operation while maintaining 12-bit resolution for IoT sensor interfaces. By combining voltage-scalable CIFF noise shaping, MSB CDEM, and last-bit majority voting, the 28-nm prototype achieves 11.2–11.7-bit ENOB over 10–50-kHz bandwidth at 0.6–1 V, enabling compact, low-power sensor readout under variable supply and bandwidth conditions. 

Process: TSMC 65 nm CMOS

Application: System-on-Chips

Publication: [IEEE JSSC'22] A Residue-Current-Locked Hybrid Low-Dropout Regulator Supporting Ultralow Dropout of Sub-50mV With Fast Settling Time Below 10 ns 

Significance:  Power  This work presents a fully integrated hybrid LDO that achieves ultralow-dropout regulation and fast load-transient response through residue-current-locked joint analog/digital control. By combining residue compensation, bounded residue control, and asynchronous DLDO activation, the 65-nm prototype achieves 20-mV-dropout operation with an 8.2-ns settling time, enabling compact high-speed power regulation for low-voltage systems. 

Process: UMC 80 nm HV CMOS

Application: Mobile Touchscreens

Publication: [IEEE ESSCIRC'19] An Always-on 0.53−13.4 mW Power-Scalable Touchscreen Controller for Ultrathin Touchscreen Displays with Current-Mode Filter and Incremental Hybrid ΔΣ ADC 

Significance:  Sensor Readout  This work presents an always-on mutual-capacitive touchscreen controller with scalable power and frame-rate operation for normal, low-power, and ultra-low-power sensing modes. By combining duty-cycled AFE operation with high-order current-mode filtering and incremental hybrid ΔΣ conversion, the prototype enables low-power touch sensing with robust display-noise immunity for mobile touchscreen systems. 

Process: TSMC 180 nm CMOS

Application: Energy-Harvesting Sensor Nodes

Publication: [IEEE TCAS-II'18] A 20 k-to-100kS/s Sub-μW 9.5b-ENOB Asynchronous SAR ADC for Energy-Harvesting Body Sensor Node SoCs in 0.18-μm CMOS 

Significance:  Data Converter  This work presents a dual-supply asynchronous SAR ADC that improves energy efficiency for energy-harvesting body sensor node SoCs. By enabling timing-calibration-free operation under scalable supply voltages, the 0.18-μm prototype achieves 9.64-bit ENOB at 100 kS/s with 562-nW power consumption, supporting low-power high-resolution biosignal acquisition.