Young-kyu Choi / 최영규
I am a tenure-track Assistant Professor in the Department of Computer Engineering at Inha University, Korea. I am actively looking for motivated PhD/MS students. International students are welcomed.
인하대학교 컴퓨터공학과 조교수로 재직 중 입니다. 함께 연구할 박사/석사 학생을 찾고 있습니다.
I received my Ph.D. degree in computer science at the University of California, Los Angeles (UCLA) in 2019. I received my B.S. and M.S. degrees in electrical engineering from Seoul National University. I joined Inha University in 2021, and I worked as a postdoctoral researcher in UCLA from 2019 to 2021. I developed TV receivers at LG Electronics from 2008 to 2011 and FPGA performance estimation tools at Falcon Computing Solutions in 2017. My research interests center around high-level synthesis (HLS) and Field-Programmable Gate Arrays (FPGAs).
E-mail: ykc (at) inha.ac.kr
High-Level Synthesis Youtube Lecture Series
For lecture notes, please go to the Teaching tab.
Ongoing Research Projects
Bridging accelerators with high-bandwidth memory (HBM Connect) [C12, A1]
Related video: https://dl.acm.org/doi/10.1145/3431920.3439301 (20 mins)
With the recent release of High Bandwidth Memory (HBM) based FPGA boards such as Xilinx Alveo boards and Intel Stratix 10 MX boards, developers can now exploit unprecedented external memory bandwidth. However, fully utilizing the available bandwidth may not be an easy task. We found a limitation in existing high-level synthesis (HLS) programming environment when multiple processing elements to access multiple HBM channels. To solve this problem, we developed HBM Connect, a high-performance customized interconnect for FPGA HBM board. We propose novel HLS-based optimization techniques to increase the throughput of AXI bus masters and switching elements. Also, we present a high-performance customized crossbar that may fully replace the built-in crossbar. We explore several design spaces and find the design point with the best resource-performance trade-off. This project will help FPGA programmers to maximize the bandwidth between accelerators and HBM.
Extending high-level synthesis for task-parallel programs (TAPA) [J8, C13]
Even though high-level synthesis (HLS) is becoming more popular, it remains a challenge to adopt the highly productive high-level programming approach for applications where coarse-grained tasks run in parallel and communicate with each other at a fine-grained level. The productivity is greatly limited due to the poor programmability, restrictions in software simulation, and slow code generation. In this project, we extend the HLS C++ language and present a fully automated framework with programmer-friendly interfaces, unconstrained software simulation, and fast hierarchical code generation to overcome these limitations and demonstrate how task-parallel programs can be productively supported in HLS. On top of TAPA, we add TARO framework which automatically simplifies the control logic (free-running optimization) without degrading the clock frequency or the performance.
Completed research projects are described in "Completed Projects" tab.