Journal

*Corresponding Author  **First Author

2026

[118] J. Seo**, S. Yeo**, Y. J. Yoon*, and K. Kim* "Defect evolution comparison between He+ and He2+ ions irradiation on graphene" Journal of the Korean Physical Society.

[117] K. H. Kim**, K. M. Kim, J. H. Moon, Y. J. Yoon*, and J. H. Seo* "Radiation-Induced Degradation and Charge-Collection Stability in 4H-SiC p-i-n Betavoltaic Cells" International Journal of Energy Research vol. 2026, p. 2227749.

[116] K. M. Kim**, K. H. Kim, S. Y. Woo, J. H. Moon, Y. J. Yoon*, and J. H. Seo* "Optimization and experimental demonstration of mesh-patterned 4H-SiC betavoltaic cells for enhanced power density" Scientific Reports vol. 16, p. 11906.

[115] 남기태**, 류연직, 차주현, 신동희, 서재화, 김경희, 윤영준*, "양성자 조사와 전극 구조에 따른 SiC PIN 소자의 자외선 응답 안정성 및 자가발전형 UV 센서 응용 가능성" 전기전자학회논문지  vol.30, pp. 142-151.

[114] 김영환**, 윤영준*, "Fe+ 이온주입을 통한 PLA 필름의 표면 개질" 한국산업정보학회논문지 vol. 31, pp. 29-37.

[113] K. Kim**, S. Y. Woo, J. H. Moon, Y. J. Yoon*, and J. H. Seo* "Robust C-V Ratio Technique for Profiling Defects in Proton-Irradiated 4H-SiC" Adv. Electron. Mater. vol. 12, p. e00601.

[112] G. S. Yun**, J. Park, W. S. Koh,  S. B. Song, K. M. Lim, S. H. Lee,  Y. J. Yoon*, and I. M. Kang* "Hydrogen-passivated AlGaN/GaN HEMTs: fabrication and electrical characterization under-proton irradiation" Results Phys. vol. 81, p. 108577.

2025

[111] S. Yeo**, J. Seo,  Y. J. Yoon*, and K. Kim* "Quantitative modeling of the non-monotonic sensitivity of defect-engineered graphene sensros"  Sci. Rep. 15, 43986.

[110] S. B. Song**, J. Park, W. S. Koh, G. S. Yun, K. M. Lim, J. Jang, J. H. Bae, S. H. Lee,  Y. J. Yoon, and I. M. Kang* "Design and analysis of 3D stacked nanosheet-based capacitorless DRAM with separated storage regions under process variations" J. Sci. 10, 101047.

[109] S. H. Lee**, J. Park,  Y. J. Yoon*, and I. M. Kang "Investigating Quasi-Nonvolatile Memory Behavior in Junctionless Field-Effect Transistors with SOI-Like Structure" Silicon 17, 4547.

[108] K. M. Kim**, I. M. Kang, J. H. Seo*, Y. J. Yoon*, and K. Kim* "Structural Optimization and Trap Effects on the Output Performance of 4H-SiC Batavoltaic Cell" Nanomaterials 15, 1625.

[107] 최규호**, 우성윤, 김기범*, 윤영준*, 서재화* "고에너지 양성자 조사 하 SiC MOSFET의 SEE 민감도 및 고전압 항복 메커니즘 실시간 평가" 전자공학회논문지 vol. 62, pp.1-7.

[106] K. H. Kim**, I. M. Kang, Y. J. Yoon*, and K. Kim* "Impact of Grain Boundaries on Zero-Temperature Coefficient Characteristics in a 3D-Stacked Transistor" Electronics 14, 3494.

[105] 김영환**, 여순목, 김기범*, 윤영준*, "Bernas형 이온주입장치의 시계열 딥러닝을 위한 Gradient Consistency-Based Window Size 최적화" 한국산업정보학회논문지 30, 1.

[104] T. S. Kwon**, Y. J. Yoon, D. Y. Park, J.-H. Bae, Y. S. Song, H. W. Kim, J. W. Seo*, and S. Y. Woo*, "Structurally optimized SiC CMOS FinFET for high-temperature and low-power SoC logic integration" Sci. Rep. 15, 28158.

[103] K. H. Kim**, K. M. Kim, Y. H. Kim, J. B. Im, G. H. Choi, I. M. Kang, and Y. J. Yoon*, "Optimization of One-transistor (1T) DRAM Using Device Parameters-dependent Zero-temperature Coefficient Point" J. Semicond. Technol. Sci. 25, 274.

[102] 장태훈**, 구대범, 이훈근, 김기범*, 윤영준*, "지형 극복 및 객체 탐지 기반 다목적 탐사 로봇 시스템의 구현" 한국산업정보학회논문지 30, 13.

[101] J. Park**, S. H. Lee, I. M. Kang, and Y. J. Yoon*, "Fabrication of AlGaN/GaN HEMT using TMAH pre-treatment and analysis of electrical characteristics by proton irradiation" Curr. Appl. Phys. 75, 33.

[100] S. R. Jeon**, S. H. Lee, J. Park, M. S. Kim, S. J. Bae, J. W. Hong, W. S. Koh, G. S. Yun, I. M. Kang*, and Y. J. Yoon*, "Experimental and Simulation Study on the Electrical Characteristics of Proton-irradiated AlGaN/GaN HEMT" J. Semicond. Technol. Sci. 25, 21.

[99] J. H. Seo**, Y. J. Kim, I. H. Kang, J. H. Moon, Y.-M. Kim, Y. J. Yoon*, and H. W. Kim*, "Degeneration mechanism of 30 MeV and 100 MeV proton irradiation effects on 1.2 kV SiC MOSFETs" Radiat. Phys. Chem. 227, 112378.

2024

[98] 김경희**, 김경민, 김영환, 임종범, 최규호, 강인만, 윤영준*, "트랜지스터의 온도 계수를 고려한 커패시터리스 디램의 설계 최적화" 전기전자학회논문지 28, 369.

[97] Y. J. Kim**, Y. Moon, J. H. Moon, H. W. Kim, W. Bahng, H. Park, Y. J. Yoon*, and J. H. Seo*, "Displacement damage effect of proton irradiation on vertical B-Ga2O3 and SiC Schottky barrier diodes (SBDs)" J. Sci. 9, 100765.

[96] 김영환**, 최규호, 김경민, 김경희, 임종범, 황용석, 윤영준*, "이온주입장치의 인출전류 예측을 위한 맞춤형 데이터 전처리 기법 및 인공지능 모델 개발" Journal of Korea Multimedia Society 27, 1023.

[95] M. S. Kim**, S. H. Lee, J. Park, S. R. Jeon, S. J. Bae, J. W. Hong, J. Jang, J.-H. Bae, Y. J. Yoon, and I. M. Kang*, "Statistical Analysis of Increased Immunity to Poly-Si Grain Boundaries in Nanosheet CMOS Logic Inverter Through Sheet Stacking" Silicon.

[94] J. Park**, S. H. Lee, S. R. Jeon, M. S. Kim, S. J. Bae, J. W. Hong, G. S. Yun, W. S. Koh, J. Jang, J.-H. Bae, Y. J. Yoon, and I. M. Kang*, "Statistical analysis of vertically stacked nanosheet complementary FET based on polycrystalline silicon with multiple grain boundaries" Results Phys. 63, 107873.

[93] J. M. Ha**, S. H. Lee**, D. Park, Y. J. Yoon, I. M. Yang, J. Seo, Y. S. Hwang, C. Y. Lee, J. K. Suk, J. K. Park, and S. Yeo*, "Synthesis mechanism from graphene quantum dots to carbon nanotubes by ion-sputtering assisted chemical vapor deposition" Discover Nano 19, 83.

[92] S. Yeo**, J. M. C, G. Kang, C. Kim, G. W. Jeon, and Y. J. Yoon*, "Transient Superhydrophilic Surface Modification of Polyimide by Metal Ion Beam Irradiation" Langmuir 40, 12200.

[91] J. H. Heo**, S. H. Lee, J. Park, G. E. Kang, Y. J. Yoon*, and I. M. Kang*, "Fabrication of recessed-gate AlGaN/GaN MOSFETs using TMAH wet etching with Cu ion implantation" Results Phys. 40, 107701.

[90] S. H. Lee**, J. Park, Y. J. Yoon*, and I. M. Kang*, "Capacitorless One-Transistor Dynamic Random-Access Memory with Novel Mechanism: Self-Refreshing" Nanomaterials 14, 179. 

2023

[89] S. H. Lee**, J. Park, G. U. Kim, G. E. Kang, J. H. Heo, S. R. Jeon, Y. J. Yoon, J. H. Seo, J. Jang, J.-H. Bae, S.-H. Lee, and I. M. Kang*, "Bulk-fin field-effect transistor-based capacitorless dynamic random-access memory and its immunity to the work-function variation effect" Japanese Journal of Applied Physics 62, SC1016. 

2022

[88] H. Roh**, Y. J. Yoon**, J. S. Park**, D.-H. Kang**, S. M. Kwak, B. C. Lee, and M. Im*, "Fabrication of High-Density Out-of-Plane Microneedle Arrays with Various Heights and Diverse Cross-Sectional Shapes" Nano-Micro Letters 14, 24.

[87] H. D. An**, S. H. Lee, J. Park, S. R. Min, G. U. Kim, Y. J. Yoon, J. H. Seo, M. S. Cho, J. Jang, J.-H. Bae, S.-H. Lee, and I. M. Kang*, "Analysis and Optimization for Characteristics of Vertical GaN Junctionless MOSFETs Depending on Specifications of GaN Substrates" Journal of Electrical Engineering & Technology 17, 3487.

[86] H. D. An**, S. H. Lee, J. Park, S. R. Min, G. U. Kim, Y. J. Yoon, J. H. Seo, M. S. Cho, J. Jang, J.-H. Bae, S.-H. Lee, and I. M. Kang*, "Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure" Nanomaterials 12, 3526.

[85] G. U. Kim**, Y. J. Yoon, J. H. Seo, S. H. Lee, J. Park, G. E. Kang, J. H. Heo, J. Jang, J.-H. Bae, S.-H. Lee, and I. M. Kang*, "Design of a Capacitorless DRAM Based on Storage Layer Separated Using Separation Oxide and Polycrystalline Silicon" Electronics 11, 3365.

[84] S. R. Min**, S. H. Lee, J. Park, G. U. Kim, G. E. Kang, J. H. Heo, Y. J. Yoon, J. H. Seo, J. Jang, J.-H. Bae, S.-H. Lee, and I. M. Kang*, "Simulation of CMOS logic inverter based on vertically stacked polycrystalline silicon nanosheet gate-all-around MOSFET and its electrical characteristics" Current Applied Physics 43, 106.

[83] H. D. An**, S. R. Min, S. H. Lee, J. Park, G. U. Kim, Y. J. Yoon, J. H. Seo, M. S. Cho, J. Jang, J.-H. Bae, S.-H. Lee, and I. M. Kang*, "Fabrication and Performances of Recessed Gate AlGaN/GaN MOSFETs with Si3N4/TiO2 Stacked Dual Gate Dielectric" Journal of Semiconductor Technology and Science 22, 105.

[82] S.-R. Min**, M.-S. Cho, S.-H. Lee, J. Park, H.-D. An, G.-U. Kim, Y.-J. Yoon, J.-H. Seo, J.-W. Jang, J.-H. Bae, S.-H. Lee, and I.-M. Kang*, "Analysis for DC and RF Characteristics Recessed-Gate GaN MOSFET Using Stacked TiO2/Si3N4 Dual-Layer Insulator" Materials 15, 819.

[81] J. M. Ha**, N. E. Lee, Y. J. Yoon, S. H. Lee, Y. S. Hwang, J. K. Suk, C. Y. Lee, C. R. Kim, and S. Yeo*, "Universal dry synthesis and patterning of high-quality and -qurity graphene quantum dots by ion-beam assisted chemical vapor deposition" Canbon 186, 28.

2021

[80] J. Park**, M. S. Cho, S. H. Lee, H. D. An, S. R. Min, G. U. Kim, Y. J. Yoon, J. H. Seo, S.-H. Lee, J. Jang, J.-H. Bae, and I. M. Kang*,  "Design of Capacitorless DRAM Based on Polyscrystalline Silicon Nanotube Structure" IEEE Access vol. 9, pp. 163675-163685.

[79]  D.-S. Kim**, Y. J. Yoon, J. S. Lee, I. M. Kang, and J.-H. Lee*, "Experimental and simulation study of power performance improvement of GaN PIN betavoltaic cell" International Journal of Energy Research vol. 45, pp. 17622-17630.

[78] S. H. Lee**, Y. J. Yoon, J. H. Seo, M. S. Cho, J. Park, H. D. An, S. R. Min, G. U. Kim, and I. M. Kang*,  "Effect of Work-function Variation on Transfer Characteristics and Memory Performances for Gate-all-around JLFET based Capacitorless DRAM" J. Semicond. Technol. Sci. vol. 21, pp. 381-389.

[77] G. U. Kim**, Y. J. Yoon, J. H. Seo, M. S. Cho, S. H. Lee, J. Park, H. D. An, S. R. Min, and I. M. Kang*,  "Electrical Performance of GaN-based Vertical Trench MOSFETs with Cylindrical and Hexagonal Structure" J. Semicond. Technol. Sci. vol. 21, pp. 398-405.

[76] M. S. Cho**, S. H. Lee, H. D. An, J. Park, S. R. Min, G. U. Kim, Y. J. Yoon, J. H. Seo, and I. M. Kang*,  "Design and Analysis of DC/DC Boost Converter using Vertical GaN Power Device based on Epitaxially Grown GaN on sapphire" J. Semicond. Technol. Sci. vol. 21, pp. 390-397.

[75] 윤영준**, 이재상, 김유종, 석오균, 이정희, 김동석, "질화갈륨 기반 전자소자의 고에너지 양성자 조사 영향평가를 위한 전산모사 모델링 연구" 한국방사선산업학회지 15, 275. 

[74] Y. J. Yoon**, J. S. Lee, I. M. Kang, E. J. Lee, and D.-S. Kim*, "Impact of process-dependent SiNx passivation on proton-induced degradation in GaN MIS-HEMTs" Results in Physics 31, 105013. 

[73] Y. J. Yoon**, J. S. Lee, J. K. Suk, I. M. Kang, J.  H. Lee, E. J. Lee, and D. S. Kim*, "Effects of Proton Irradiation on the Currnet Characteristics of SiN-Passivated AlGaN/GaN MIS-HEMTs Using a TMAH-Based Surface Pre-Treatment" Micromachines 12, 864. 

[72] Y. J. Yoon**, J. S. Lee, I. M. Kang, J.-H. Lee, and D.-S. Kim*, "Design optimization of GaN Diode with p-GaN multi-well structure for high-efficiency betavoltaic cell" Nuclear Engineering and Technology 53, 1284.

[71] Y. J. Yoon*, **, J. S. Lee, I. M. Kang, and D.-S. Kim, "Single-event transient characteristics of vertical gate-all-around junctionless field-effect transistor on bulk substrate" Applied Physics A 127, 77.

[70] D.-S. Kim**, J.-G. Kim, J.-H. Lee, Y. S. Hwang,  Y. J. Yoon, J. S. Lee, Y. Bae, and J.-H. Lee*, "Mechanism of Proton-Induced electrical degradation of AlGaN/GaN high electron mobility transistors" Solid State Electronics 175, 107957.

[69]  Y. J. Yoon**, J. S. Lee, I. M. Kang, J.-H. Lee, and D.-S. Kim*, "Design and optimization of GaN-based betavoltaic cell for enhanced output power density" International Journal of Energy Research 45, 799.

2020

[68] W. D. Jang**, Y. J. Yoon, M. S. Cho, J. H. Jung, S. H. Lee, J. Jang, J.-H. Bae, and I. M. Kang*, "Design and Analysis of Metal-Oxide-Semiconductor Field-Effect Transistor-Based Capacitorless One-Transistor Embedded Dynamic Random-Access Memory with Double-Polysilicon Layer Using Grain Boundary for Hole Storage" Journal of Nanoscience and Nanotechnology vol. 20, pp. 6596-6602.

[67] Y.-J. Nam**, Y. J. Yoon, S.-K. Lee, M. Im*, and J.-H. Park*, "Fabrication of Glass Micropipette Device using Reflow Processes and Its Integration With Microfluidic Channels for Patch Clamp Recording of Cell" IEEE Sensors Journal vol. 20, pp. 14694-14702.

[66] Y. J. Yoon**, J. S. Lee, D.-S. Kim, S. H. Lee, and I. M. Kang*, "One-Transistor Dynamic Random-Access Memory Based on Gate-All-Around Junction-Less Field-Effect Transistor with a Si/SiGe Heterostructure" Electronics 9, 2134.

[65] Y. J. Yoon**, J. S. Lee, I. M. Kang, J.  H. Lee, and D. S. Kim*, "Design and Analysis of Gallium Nitride-Based p-i-n Diode Structure for Betavoltaic Cell with Enhanced Output Power Density" Micromachines 11, 1100. 

[64] J. H. Jung**, M. S. Cho, W. D. Jang, S. H. Lee, J. Jang, J.-H. Bae, Y. J. Yoon*, and I. M. Kang*, "Fabrication of AlGaN/GaN MISHEMT with the dual-metal gate electrode and its performances" Applied Physics A 126, 274. 

[63] Y. J. Yoon**, J.-I. Lee**, Y. J. Jang, S. An, J. H. Kim, S. I. Fried, and M. Im*, "Retinal Degeneration Reduces Consistency of Network-Mediated Responses Arising in Ganglion Cells to Electric Stimulation" IEEE Transactions on Neural Systems and Rehabilitation Engineering 28, 1921. 

[62] Y. J. Yoon**, J. S. Lee, D.-S. Kim, J.-H. Lee, and I. M. Kang*, "Gallium Nitride Normally Off MOSFET Using Dual-Metal-Gate Structure for the Improvement in Current Drivability" Electronics 9, 1402.

[61] W. D. Jang**, Y. J. Yoon, M. S. Cho, J. H. Jung, S. H. Lee, J. Jang, J.-H. Bae, and I. M. Kang*, "Polycrystalline silicon metal-oxide-semiconductor field-effect transistor-based stacked multi-layer one-transistor dynamic random-access memory with double-gate structure for the embedded systems" Japanese Journal of Applied Physics vol. 59, p. SGGB01.

[60] D.-S. Kim**, J.-H. Lee, J.-G. Kim, Y. J. Yoon, J. S. Lee, and J.-H. Lee*, "Anomalous DC Characteristics of AlGaN/GaN HEMTs Depending on Proton Irradiation Energies" ECS Journal of Solid State Science and Technology vol. 9, p. 065005.

2019

[59] W. D. Jang**, Y. J. Yoon, M. S. Cho, B. G. Kim, and I. M. Kang*, "Effect of Interface Traps on the Device Performance of InGaAs-Based Gate-All-Around Tunneling Field-Effect Transistors" Journal of Nanoscience and Nanotechnology vol. 19, pp. 6036-6042.

[58] M. S. Cho**, Y. J. Yoon, B. G. Kim, J. H. Jung, W. D. Jang, J.-H. Lee, and I. M. Kang*, "Simulation for Electrical Performances of the Capacitorless Dynamic Random Access Memory Based on Junctionless FinFETs" Journal of Nanoscience and Nanotechnology vol. 19, pp. 6755-6761.

[57] B. G. Kim**, J. H. Seo, Y. J. Yoon, M. S. Cho, and I. M. Kang*, "Design Optimization of InGaAs/GaAsSb-Based P-Type Gate-All-Around Arch-Shaped Tunneling Field-Effect Transistor" Journal of Nanoscience and Nanotechnology vol. 19, pp. 6762-6766.

[56] J. H. Jung**, Y. J. Yoon, M. S. Cho, B. G. Jang, W. D. Jang, and I. M. Kang*, "Analysis of Electrical Characteristics of InAlGaN/GaN-based High Electron Mobility Transistors with AlGaN Back Barriers" Journal of Nanoscience and Nanotechnology vol. 19, pp. 6008-6015.

[55] J. H. Seo**, Y. J. Yoon, S. Cho, I. M. Kang*, and J.-H. Lee, "Design Optimization and Analysis of InGaAs/InAs/InGaAs Heterojunction-Based Electron Hole Bilayer Tunneling FETs" Journal of Nanoscience and Nanotechnology vol. 19, pp. 6070-6076.

[54] Y. J. Yoon**, M. S. Cho, B. G. Kim, J. H. Seo, and I. M. Kang*, "Capacitorless One-Transistor Dynamic Random-Access Memory Based on Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor with Si/SiGe Heterojunction and Underlap Structure for Improvement of Sensing Margin and Retention Time" Journal of Nanoscience and Nanotechnology vol. 19, pp. 6023-6030.

[53] W. D. Jang**, Y. J. Yoon, M. S. Cho, J. H. Jung, S. H. Lee, J. Jang, J.-H. Bae, and I. M. Kang*, "Design and Optimization of Germanium-Based Gate-Metal-Core Vertical Nanowire Tunnel FET" Micromachines 10, 749.

[52] Y. J. Yoon**, J. H. Seo**, S. Cho, J.-H. Lee, and I. M. Kang*, "A polycrystalline-silicon dual-gate MOSFET-based 1T-DRAM using grain boundary-induced variable resistance" Applied Physics Letters 144, 183503.

[51] J. H. Seo**, Y. J. Yoon**, E. Yu, W. Sun, H. Shin, I. M. Kang, J.-H Lee*, and S. Cho*, "Fabrication and Characterization of a Thin-Body Poly-Si 1T DRAM With Charge-Trap Effect" IEEE Electron Device Letters vol. 40, pp. 566-569.

[50] Q. Dai**, D.-H. Son, Y.-J. Yoon, J.-G. Kim, X. Jin, I.-M. Kang, D.-H. Kim, Y. Xu, S. Cristoloveanu, and J.-H Lee*, "Deep Sub-60 mV/decade Subthreshold Swing in AlGaN/GaN FinMISHFETs with M-Plane Sidewall Channel" IEEE Transactions on Electron Devices 66, 1699.

[49] M. S. Cho**, Y.-J. Yoon, S. Cho, and I.-M. Kang, "Design and Analysis of logic inverter using antimonide-based compound semiconductor junctionless transistor" Applied Physics A vol. 125, p. 173.

2018

[48] G. B. Gyeong**, J. H. Seo, Y. J. Yoon, M. S. Cho, E. Yu, J.-H. Lee, S. Cho, and I. M. Kang*, "Simulation of One-Transistor Dynamic Random-Access Memory Based on Symmetric Double-Gate Si Junctionless Transistor" Journal of Nanoscience and Nanotechnology vol. 18, pp. 6593-6597.

[47] J. H. Seo**, Y. J. Yoon, and I. M. Kang*, "Design Optimization of Ge/GaAs-Based Heterojunction Gate-All-Around (GAA) Arch-Shaped Tunneling Field-Effect Transistor (A-TFET)" Journal of Nanoscience and Nanotechnology vol. 18, pp. 6602-6605.

[46] J. H. Seo**, Y. J. Yoon, D.-H. Son, J.-G. Kim, J.-H. Lee, J.-H. Lee, K.-S. Im, and I. M. Kang*, "A Novel Analysis of Lgd Dependent-1/f Noise in In0.08Al0.92N/GaN" IEEE Electron Device Letters vol. 39, pp. 1552-1555. 

[45] Y. J. Yoon**, J. H. Seo, and I. M. Kang*, "Performance comparison betweeon p-i-n and p-n junction tunneling field-effect transistors" Japanese Journal of Applied Physics vol. 57, p. 06HC01. 

[44] Y. J. Yoon**, J. H. Seo, and I. M. Kang*, "Capacitorless one-transistor dynamic random access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure" Japanese Journal of Applied Physics vol.57, p.04FG03. 

2017

[43] M. S. Cho**, R. H. Kwon, J. H. Seo, Y. J. Yoon, Y. I. Jang, C.-H. Won, J.-G. Kim, J. Lee, S. Cho, J.-H. Lee, and I. M. Kang*, "Electrical Performances of InN/GaN Tunneling Field-Effect Transistor" Journal of Nanoscience and Nanotechnology vol. 17, pp. 8355-8359.

[42] J. H. Seo**, Y. J. Yoon, J.-H. Lee, and I. M. Kang*, "Design Optimization and Analysis of InGaAs-Based Gate-All-Around (GAA) Junctionless Field-Effect Transistor (JLFET)" Journal of Nanoscience and Nanotechnology vol. 17, pp. 8350-8354.

[41] B. G. Kim**, R. H. Kwon, J. H. Seo,  Y. J. Yoon, Y. I. Jang, M. S. Cho, J.-H. Lee, S. Cho, and I. M. Kang*, "Electrical Characteristics of Tunneling Field-effect Transistors using Vertical Tunneling Operation Based on AlGaSb/InGaAs" Jounral of Electrical Engineering & Technology vol. 12, pp. 2324-2332.

[40] Y. J. Yoon**, J. H. Seo, J.-H. Lee, and I. M. Kang*, "GaN-Based Junctionless Field-Effect Transistor with Hetero-Gate Dielectric for Enhancement of Direct Current and Radio Frequency Performance" Journal of Nanoelectronics and Optoelectronics vol. 12, pp. 1114-1118.

[39] Y. J. Yoon**, J. H. Seo, M. S. Cho, J.-H. Lee, and I. M. Kang*, "Effect of Electric Fringe-Field  on Low-Power and Radio-Frequency Performances of Sub-10 nm Junctionless Transistors with Hetero-Dielectric Spacer Structure" Journal of Nanoscience and Nanotechnology vol. 17, pp. 7140-7144.

[38] Y. J. Yoon**, J. H. Seo, M. S. Cho, B. G. Kim, S. H. Lee, and I. M. Kang*, "Capacitorless one-transistor dynamic random access memory based on double-gate GaAs junctionless transistor" Japanese Journal of Applied Physics 56, 06GF01. 

[37] R. H. Kwon**, S. H. Lee**, Y. J. Yoon, J. H. Seo, Y. I. Jang, M. S. Cho, B. G. Kim, J.-H. Lee and I. M. Kang*, "InGaAs-based Tunneling Field-effect Transistor with Stacked Dual-metal-Gate with PNPN Structure for High Performance" Journal of Semiconductor Technology and Science vol. 17, pp. 230-238.

[36] Y. I. Jang**, S. H. Lee, J. H. Seo, Y. J. Yoon, R. H. Kwon, M. S. Cho, B. G. Kim, G. M. Yoo, J.-H. Lee and I. M. Kang*, "Design and Analysis of AlGaN/GaN MIS HEMTs with a Dual-metal-gate Structure" Journal of Semiconductor Technology and Science vol. 17, pp. 223-229.

2016

[35] H. S. Kang**, J. H. Seo,  Y. J. Yoon, M. S. Cho, and I. M. Kang*, "DC and RF analysis of geometrical parameter changes in the current aperture vertical electron transistor" Jounral of Electrical Engineering & Technology vol. 11, pp. 1763-1768.

[34] Y. J. Yoon**, J. H. Seo, M. S. Cho, H.-S. Kang, C.-H. Won,  I. M. Kang*, and J.-H. Lee*, "TMAH-based wet surface pre-treatment for reduction of leakage current in AlGaN/GaN MIS-HEMTs" Solid-State Electronics 124, 54.  Editor's Choice Selection

[33] R. H. Kwon**, H. R. Eun, J. H. Seo, Y. J. Yoon, Y. I. Jang, J.-H. Lee, and I. M. Kang*, "Design Optimization of AlN/GaN Based Double-Heterojunction Fin-Type High Electron Mobility Transistors for High On-State Current" Journal of Nanoscience and Nanotechnology vol. 16, pp. 10193-10198. 

[32] Y. J. Yoon**, J. H. Seo, H.-I. Kwon, J.-H. Lee, and I. M. Kang*, "Enhancement-Mode GaN-Based Junctionless Vertical Surrounding-Gate Transistor with Dual-Material Gate Structure for High-Frequency Applications" Journal of Nanoscience and Nanotechnology vol. 16, pp. 10204-10209.

[31] M. S. Cho**, J. H. Seo, Y. J. Yoon, J.-H. Lee, and I. M. Kang*, "Design Optimization and Analysis of InGaAs-Based Junctionless Fin Type Field-Effect Transistors (FinFETs) with LG = 10 nm" Journal of Nanoscience and Nanotechnology vol. 16, pp. 10187-10192. 

[30] J. H. Seo**, Y. J. Yoon, Y.-W. Jo, D.-H. Son, S. Cho, H.-I. Kwon, J.-H. Lee, and I. M. Kang*, "Design Optimization of InAs-based Gate-All-Around(GAA) Arch-Shaped Tunneling Field-Effect Transistor(TFET)" Journal of Nanoscience and Nanotechnology vol. 16, pp. 10199-10203. 

[29] E. R. Eun**, Y. J. Yoon, J. H. Seo, M. S. Cho, J.-H. Lee, H.-I. Kwon, and I. M. Kang*, "Design optimization of vertical nanowire tunneling field-effect transistor based on AlGaSb/InGaAs heterojunction layer" Current Applied Physics vol. 16, pp. 681-685. 

[28] J. H. Seo**, Y.-W. Jo, Y. J. Yoon , D.-H. Son, C.-H. Won, H. S. Jang, I. M. Kang*, and J.-H. Lee*, "Al(In)N/GaN Fin-Type HEMT With Very-Low Laekage Current and Enhanced I-V Characteristic for Switching Applications" IEEE Electron Device Letters vol. 37, pp. 855-858. 

[27] Y. J. Yoon**, J. H. Seo, S. Cho, H.-I. Kwon, J.-H. Lee, and I. M. Kang*, "Effects of dual-spacer dielectrics on low-power and high-speed performance of sub-10 nm tunneling field-effect transistors" Japanese Journal of Applied Physics vol. 55, p. 06GG02. 

[26] Y. J. Yoon**, J. H. Seo, S. Cho, H.-I Kwon*, J.-H. Lee and I. M. Kang*, "Sub-10 nm Ge/Ga Heterojunction-Based Tunneling Field-Effect Transistor with Vertical Tunneling Operation for Ultra-Low-Power Applications" Journal of Semiconductor Technology and Science vol. 16, pp. 172-178. 

2015

[25] S. Y. Kim**, J. H. Seo, Y. J. Yoon, H.-Y. Lee, S. M. Lee, S. Cho, and I. M. Kang*, "Design and Analysis of CMOS-Compatible III-V Compound Electron-Hole Bilayer Tunneling Field-Effect Transistor for Ultra-Low-Power Applications" Journal of Nanoscience and Nanotechnology vol. 15, pp. 7486-7492. 

[24] Y. J. Yoon**, H. R. Eun, J. H. Seo, H.-S. Kang, S. M. Lee, J. Lee, S. Cho*, H.-S. Tae, J.-H. Lee, and I. M. Kang*, "Short-Channel Tunneling Field-Effect Transistor with Drain-Overlap and Dual-Metal Gate Structure for Low-Power and High-Speed Operations" Journal of Nanoscience and Nanotechnology vol. 15, 7430-7435. 

[23] Y. I. Jang**, J. H. Seo, Y. J. Yoon, H. R. Eun, R. H. Kwon, J-H. Lee, H.-I Kwon* and I. M. Kang*, "Design and Analysis of Gate-recessed AlGaN/GaN Fin-type Field-Effect Transistor" Journal of Semiconductor Technology and Science vol. 15, pp. 554-562. 

[22] J. H. Seo**, Y. J. Yoon, S. Cho, H.-S. Tae, J.-H. Lee and I. M. Kang*, "Analyses on RF Performances of Silicon-Compatible InGaAs-Based Planar-Type and Fin-Type Junctionless Field-Effect Transistors" Journal of Nanoscience and Nanotechnology 15, pp.  7615-7619. 

[21] S. Y. Kim**, J. H. Seo,  Y. J. Yoon, J.-S. Kim, S. Cho, J.-H. Lee, and I. M. Kang*, "Electrical Characteristics of Enhancement-Mode n-Channel Vertical GaN MOSFETs and the Effects of Sidewall Slope" Jounral of Electrical Engineering & Technology vol. 10, pp. 1131-1137.

[20] H.-S. Kang**, C.-H. Won, Y.-J. Kim, D.-S. Kim,  Y. J. Yoon, I. M. Kang, Y. S. Lee, and J.-H. Lee*, "Suppression of current collapse in AlGaN/GaN MISHFET with carbon-doped GaN/undoped GaN multi-layered buffer structure" Physica Status Solidi (a) vol. 212, pp. 1116-1121.

[19] J. H. Seo**, Y. J. Yoon, S. Lee,  J.-H. Lee, S. Cho*, and I. M. Kang*, "Design and analysis of Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET)" Current Applied Physics 15, 208. 

[18] J. S. Kim**, Y. J. Yoon, J. H. Seo,  Y. I. Jang, J.-H. Lee, S. Cho, G. M. Yoo, and I. M. Kang*, "High-performance Ge/GaAs heterojunction tunneling FET with a channel engineering for sub-0.5 V operation" Semiconductor Science and Technology vol. 30, p. 035020. 

[17] Y. J. Kim**, Y. J. Yoon, J. H. Seo,  S. M. Lee, S. Cho, J.-H. Lee, and I. M. Kang*, "Effect of Ga fraction in InGaAs Channel on performances of gate-all-around tunneling field-effect transistor" Semiconductor Science and Technology vol. 30, p. 015006. 

2014

[16] K.-S. Im**, J. H. Seo, Y. J. Yoon, Y. I. Jnag, J. S. Kim, S. Cho, J.-H. Lee, S. Cristoloveanu, J.-H. Lee, and I. M. Kang*, "GaN junctionless trigate field-effect transistor with deep-submicron gate length: Characterization and modeling in RF regime" Japanese Journal of Applied Physics 53, 118001. 

[15] H. B. Roh**, J. H. Seo, Y. J. Yoon, J. H. Bae, E.-S. Cho, J.-H. Lee, S. Cho, and I. M. Kang*, "Evaluation of Radio-Frequency Performance of Gate-All-Around Ge/GaAs Heterojunction Tunneling Field-Effect  Transistor with Hetero-Gate-Dielectric by Mixed-Mode Simulation" Journals of Electrical Engineering & Technology vol. 9, pp.2070-2078. 

[14] J. H. Seo**, Y. J. Yoon, H. G. Lee, G. W. Yoo, Y.-W. Jo, D.-H. Son, J.-H. Lee, E.-S. Cho, S. Cho, and I. M. Kang*, "Design and analysis of vertical-channel Gallium Nitride (GaN) junctionless nanowire transistors (JNT)" Journals of Nanoscience and Nanotechnology 14, pp.8130-8135. 

[13] J. H. Seo**, Y. J. Yoon, H. G. Lee, G. W. Yoo, E.-S. Cho, S. Cho, J.-H. Lee, and I. M. Kang*, "A reliable extraction method for source and drain series resistances in silicon nanowire metal-oxide-semiconductor field-effect-transistors (MOSFETs) based on Radio-Frequency Analysis" Journals of Nanoscience and Nanotechnology 14, pp.8219-8224. 

[12] H. G. Lee**, J. H. Seo, Y. J. Yoon, Y. J. Kim, J. Kim, S. Cho, E.-S. Cho, J.-H. Bae, J.-H. Lee, and I. M. Kang*,  "Fabrication and Characterization of GaN-based Light-emitting Diode (LED) with Triangle-type Structure" Molecular Crystals and Liquid Crystals vol. 599, pp. 163-169. 

[11] S. Y. Kim**, J. H. Seo, Y. J. Yoon, G. M. Yoo, Y. J. Kim, H. R. Eun, H. S. Kang, J. Kim, S. Cho, J.-H. Lee, and I. M. Kang*, "Design and Analysis of Sub-10 nm Junctionless Fin-Shaped Field-Effect Transistors" Journal of Semiconductor Technology and Science vol. 14, pp. 508-517. 

[10] H.-S. Kang**, D.-S. Kim, C.-H. Won, Y.-J. Kim, Y. J. Yoon, D-K. Kim, J.-H. Lee, Y. H. Bae, and S. Cristoloveanu, "Impact of Multi-Layer Carbon-Doped/Undoped GaN Buffer on Suppression of Current Collapse in AlGaN/GaN HFETs" International Journal of High Speed Electronics and Systems 23, 1450017. 

[9] Y. J. Yoon**, H.-S. Kang, J. H. Seo, Y.-J. Kim, J.-H. Bae, J.-H. Lee, S. Cho, E.-S. Cho, and I. M. Kang*, "Design of a Recessed-gate GaN-based MOSFET Using a Dual Gate Dielectric for High-power Applications" Journal of the Korea Physical Society 65, 1579. 

[8] H. R. Eun**, S. Y. Woo, H. G. Lee, Y. J. Yoon, J. H. Seo, J.-H. Lee, J. Kim, and I. M. Kang*, "Investigation of InAs/InGaAs/InP Heterojunction Tunneling Field-Effect Transistors" Journal of Electrical Engineering & Technology 9, 1654. 

[7] S. Y. Woo**, Y. J. Yoon, J. H. Seo, G. M. Yoo, S. Cho*, and I. M. Kang*, "InGaAs/Si Heterojunction Tunneling Field-Effect Transistor on Silicon Substrate" IEICE Transactions on Electronics E97-C, 677. 

[6] Y. J. Yoon**, J. H. Seo, H.-S. Kang, Y.-J. Kim, J.-H. Bae, E.-S. Cho, J.-H. Lee, S. Cho*, and I. M. Kang*, "Effect of spacer dielectrics on performance characteristics of Ge-based tunneling field-effect transistor" Japanese Journal of Applied Physics 53, 06JE05. 

[5] Y. J. Yoon**, J. H. Seo, E.-S. Cho, J.-H. Lee, J.-H. Bae, S. Cho, and I. M. Kang*, "Heteromaterial Gate Tunneling Field-Effect Transistor for High-Speed and Radio-Frequency Applications" Journals of Nanoscience and Nanotechnology 14, 8136. 

2013

[4] S. Y. Woo**, Y. J. Yoon, S. Cho, J.-H. Lee, and I. M. Kang*, "Analysis on RF Parameters of Nanoscale Tunneling Field-Effect Transistor Based on InAs/InGaAs/InP heterojunctions" Journals of Nanoscience and Nanotechnology 13, 8133. 

[3] K. R. Kim**, Y. J. Yoon*, S. Cho, J. H. Seo, J.-H. Lee, J.-H. Bae, E.-S. Cho, and I. M. Kang*, "InGaAs/InP heterojunction-channel tunneling field-effect transistor for ultra-low operation and standby power application below supply voltage of 0.5 V" Current Applied Physics 13, 2051. 

[2] Y. J. Yoon**, S. Cho*, J. H. Seo, I. M. Kang*, B.-G. Park, and J.-H. Lee, "Compound Semiconductor Tunneling Field-Effect Transistor Based on Ge/GaAs Heterojunction with Tunneling-Boost Layer for High-Performance Operation" Japanese Journal of Applied Physics 52, 04CC04. 

2012

[1] Y. J. Yoon**, S. Y. Woo, J. H. Seo, J. S. Lee, Y. S. Park, J.-H. Lee, and I. M. Kang*, "Design Optimization of Vertical Double-gate Tunneling Field-effect Transistors" Journal of the Korea Physical Society 61, 1679.