*Corresponding Author **First Author
2025
[59] K. M. Kim**, I. M. Kang, J. H. Seo*, Y. J. Yoon*, and K. Kim* "Structural Optimization and Trap Effects on the Output Performance of 4H-SiC Batavoltaic Cell" Nanomaterials 15, 1625.
[58] K. H. Kim**, I. M. Kang, Y. J. Yoon*, and K. Kim* "Impact of Grain Boundaries on Zero-Temperature Coefficient Characteristics in a 3D-Stacked Transistor" Electronics 14, 3494.
[57] 김영환**, 여순목, 김기범*, 윤영준*, "Bernas형 이온주입장치의 시계열 딥러닝을 위한 Gradient Consistency-Based Window Size 최적화" 한국산업정보학회논문지 30, 1.
[56] T. S. Kwon**, Y. J. Yoon, D. Y. Park, J.-H. Bae, Y. S. Song, H. W. Kim, J. W. Seo*, and S. Y. Woo*, "Structurally optimized SiC CMOS FinFET for high-temperature and low-power SoC logic integration" Sci. Rep. 15, 28158.
[55] K. H. Kim**, K. M. Kim, Y. H. Kim, J. B. Im, G. H. Choi, I. M. Kang, and Y. J. Yoon*, "Optimization of One-transistor (1T) DRAM Using Device Parameters-dependent Zero-temperature Coefficient Point" J. Semicond. Technol. Sci. 25, 274.
[54] 장태훈**, 구대범, 이훈근, 김기범*, 윤영준*, "지형 극복 및 객체 탐지 기반 다목적 탐사 로봇 시스템의 구현" 한국산업정보학회논문지 30, 13.
[53] J. Park**, S. H. Lee, I. M. Kang, and Y. J. Yoon*, "Fabrication of AlGaN/GaN HEMT using TMAH pre-treatment and analysis of electrical characteristics by proton irradiation" Curr. Appl. Phys. 75, 33.
[52] S. R. Jeon**, S. H. Lee, J. Park, M. S. Kim, S. J. Bae, J. W. Hong, W. S. Koh, G. S. Yun, I. M. Kang*, and Y. J. Yoon*, "Experimental and Simulation Study on the Electrical Characteristics of Proton-irradiated AlGaN/GaN HEMT" J. Semicond. Technol. Sci. 25, 21.
[51] J. H. Seo**, Y. J. Kim, I. H. Kang, J. H. Moon, Y.-M. Kim, Y. J. Yoon*, and H. W. Kim*, "Degeneration mechanism of 30 MeV and 100 MeV proton irradiation effects on 1.2 kV SiC MOSFETs" Radiat. Phys. Chem. 227, 112378.
2024
[50] 김경희**, 김경민, 김영환, 임종범, 최규호, 강인만, 윤영준*, "트랜지스터의 온도 계수를 고려한 커패시터리스 디램의 설계 최적화" 전기전자학회논문지 28, 369.
[49] Y. J. Kim**, Y. Moon, J. H. Moon, H. W. Kim, W. Bahng, H. Park, Y. J. Yoon*, and J. H. Seo*, "Displacement damage effect of proton irradiation on vertical B-Ga2O3 and SiC Schottky barrier diodes (SBDs)" J. Sci. 9, 100765.
[48] 김영환**, 최규호, 김경민, 김경희, 임종범, 황용석, 윤영준*, "이온주입장치의 인출전류 예측을 위한 맞춤형 데이터 전처리 기법 및 인공지능 모델 개발" Journal of Korea Multimedia Society 27, 1023.
[47] M. S. Kim**, S. H. Lee, J. Park, S. R. Jeon, S. J. Bae, J. W. Hong, J. Jang, J.-H. Bae, Y. J. Yoon, and I. M. Kang*, "Statistical Analysis of Increased Immunity to Poly-Si Grain Boundaries in Nanosheet CMOS Logic Inverter Through Sheet Stacking" Silicon.
[46] J. Park**, S. H. Lee, S. R. Jeon, M. S. Kim, S. J. Bae, J. W. Hong, G. S. Yun, W. S. Koh, J. Jang, J.-H. Bae, Y. J. Yoon, and I. M. Kang*, "Statistical analysis of vertically stacked nanosheet complementary FET based on polycrystalline silicon with multiple grain boundaries" Results Phys. 63, 107873.
[45] J. M. Ha**, S. H. Lee**, D. Park, Y. J. Yoon, I. M. Yang, J. Seo, Y. S. Hwang, C. Y. Lee, J. K. Suk, J. K. Park, and S. Yeo*, "Synthesis mechanism from graphene quantum dots to carbon nanotubes by ion-sputtering assisted chemical vapor deposition" Discover Nano 19, 83.
[44] S. Yeo**, J. M. C, G. Kang, C. Kim, G. W. Jeon, and Y. J. Yoon*, "Transient Superhydrophilic Surface Modification of Polyimide by Metal Ion Beam Irradiation" Langmuir 40, 12200.
[43] J. H. Heo**, S. H. Lee, J. Park, G. E. Kang, Y. J. Yoon*, and I. M. Kang*, "Fabrication of recessed-gate AlGaN/GaN MOSFETs using TMAH wet etching with Cu ion implantation" Results Phys. 40, 107701.
[42] S. H. Lee**, J. Park, Y. J. Yoon*, and I. M. Kang*, "Capacitorless One-Transistor Dynamic Random-Access Memory with Novel Mechanism: Self-Refreshing" Nanomaterials 14, 179.
2023
[41] S. H. Lee**, J. Park, G. U. Kim, G. E. Kang, J. H. Heo, S. R. Jeon, Y. J. Yoon, J. H. Seo, J. Jang, J.-H. Bae, S.-H. Lee, and I. M. Kang*, "Bulk-fin field-effect transistor-based capacitorless dynamic random-access memory and its immunity to the work-function variation effect" Japanese Journal of Applied Physics 62, SC1016.
2022
[40] H. Roh**, Y. J. Yoon**, J. S. Park**, D.-H. Kang**, S. M. Kwak, B. C. Lee, and M. Im*, "Fabrication of High-Density Out-of-Plane Microneedle Arrays with Various Heights and Diverse Cross-Sectional Shapes" Nano-Micro Letters 14, 24.
[39] H. D. An**, S. H. Lee, J. Park, S. R. Min, G. U. Kim, Y. J. Yoon, J. H. Seo, M. S. Cho, J. Jang, J.-H. Bae, S.-H. Lee, and I. M. Kang*, "Analysis and Optimization for Characteristics of Vertical GaN Junctionless MOSFETs Depending on Specifications of GaN Substrates" Journal of Electrical Engineering & Technology 17, 3487.
[38] H. D. An**, S. H. Lee, J. Park, S. R. Min, G. U. Kim, Y. J. Yoon, J. H. Seo, M. S. Cho, J. Jang, J.-H. Bae, S.-H. Lee, and I. M. Kang*, "Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure" Nanomaterials 12, 3526.
[37] G. U. Kim**, Y. J. Yoon, J. H. Seo, S. H. Lee, J. Park, G. E. Kang, J. H. Heo, J. Jang, J.-H. Bae, S.-H. Lee, and I. M. Kang*, "Design of a Capacitorless DRAM Based on Storage Layer Separated Using Separation Oxide and Polycrystalline Silicon" Electronics 11, 3365.
[36] S. R. Min**, S. H. Lee, J. Park, G. U. Kim, G. E. Kang, J. H. Heo, Y. J. Yoon, J. H. Seo, J. Jang, J.-H. Bae, S.-H. Lee, and I. M. Kang*, "Simulation of CMOS logic inverter based on vertically stacked polycrystalline silicon nanosheet gate-all-around MOSFET and its electrical characteristics" Current Applied Physics 43, 106.
[35] H. D. An**, S. R. Min, S. H. Lee, J. Park, G. U. Kim, Y. J. Yoon, J. H. Seo, M. S. Cho, J. Jang, J.-H. Bae, S.-H. Lee, and I. M. Kang*, "Fabrication and Performances of Recessed Gate AlGaN/GaN MOSFETs with Si3N4/TiO2 Stacked Dual Gate Dielectric" Journal of Semiconductor Technology and Science 22, 105.
[34] S.-R. Min**, M.-S. Cho, S.-H. Lee, J. Park, H.-D. An, G.-U. Kim, Y.-J. Yoon, J.-H. Seo, J.-W. Jang, J.-H. Bae, S.-H. Lee, and I.-M. Kang*, "Analysis for DC and RF Characteristics Recessed-Gate GaN MOSFET Using Stacked TiO2/Si3N4 Dual-Layer Insulator" Materials 15, 819.
[33] J. M. Ha**, N. E. Lee, Y. J. Yoon, S. H. Lee, Y. S. Hwang, J. K. Suk, C. Y. Lee, C. R. Kim, and S. Yeo*, "Universal dry synthesis and patterning of high-quality and -qurity graphene quantum dots by ion-beam assisted chemical vapor deposition" Canbon 186, 28.
2021
[32] 윤영준**, 이재상, 김유종, 석오균, 이정희, 김동석, "질화갈륨 기반 전자소자의 고에너지 양성자 조사 영향평가를 위한 전산모사 모델링 연구" 한국방사선산업학회지 15, 275.
[31] Y. J. Yoon**, J. S. Lee, I. M. Kang, E. J. Lee, and D.-S. Kim*, "Impact of process-dependent SiNx passivation on proton-induced degradation in GaN MIS-HEMTs" Results in Physics 31, 105013.
[30] Y. J. Yoon**, J. S. Lee, J. K. Suk, I. M. Kang, J. H. Lee, E. J. Lee, and D. S. Kim*, "Effects of Proton Irradiation on the Currnet Characteristics of SiN-Passivated AlGaN/GaN MIS-HEMTs Using a TMAH-Based Surface Pre-Treatment" Micromachines 12, 864.
[29] Y. J. Yoon**, J. S. Lee, I. M. Kang, J.-H. Lee, and D.-S. Kim*, "Design optimization of GaN Diode with p-GaN multi-well structure for high-efficiency betavoltaic cell" Nuclear Engineering and Technology 53, 1284.
[28] Y. J. Yoon*, **, J. S. Lee, I. M. Kang, and D.-S. Kim, "Single-event transient characteristics of vertical gate-all-around junctionless field-effect transistor on bulk substrate" Applied Physics A 127, 77.
[27] D.-S. Kim**, J.-G. Kim, J.-H. Lee, Y. S. Hwang, Y. J. Yoon, J. S. Lee, Y. Bae, and J.-H. Lee*, "Mechanism of Proton-Induced electrical degradation of AlGaN/GaN high electron mobility transistors" Solid State Electronics 175, 107957.
[26] Y. J. Yoon**, J. S. Lee, I. M. Kang, J.-H. Lee, and D.-S. Kim*, "Design and optimization of GaN-based betavoltaic cell for enhanced output power density" International Journal of Energy Research 45, 799.
2020
[25] Y. J. Yoon**, J. S. Lee, D.-S. Kim, S. H. Lee, and I. M. Kang*, "One-Transistor Dynamic Random-Access Memory Based on Gate-All-Around Junction-Less Field-Effect Transistor with a Si/SiGe Heterostructure" Electronics 9, 2134.
[24] Y. J. Yoon**, J. S. Lee, I. M. Kang, J. H. Lee, and D. S. Kim*, "Design and Analysis of Gallium Nitride-Based p-i-n Diode Structure for Betavoltaic Cell with Enhanced Output Power Density" Micromachines 11, 1100.
[23] J. H. Jung**, M. S. Cho, W. D. Jang, S. H. Lee, J. Jang, J.-H. Bae, Y. J. Yoon*, and I. M. Kang*, "Fabrication of AlGaN/GaN MISHEMT with the dual-metal gate electrode and its performances" Applied Physics A 126, 274.
[22] Y. J. Yoon**, J.-I. Lee**, Y. J. Jang, S. An, J. H. Kim, S. I. Fried, and M. Im*, "Retinal Degeneration Reduces Consistency of Network-Mediated Responses Arising in Ganglion Cells to Electric Stimulation" IEEE Transactions on Neural Systems and Rehabilitation Engineering 28, 1921.
[21] Y. J. Yoon**, J. S. Lee, D.-S. Kim, J.-H. Lee, and I. M. Kang*, "Gallium Nitride Normally Off MOSFET Using Dual-Metal-Gate Structure for the Improvement in Current Drivability" Electronics 9, 1402.
2019
[20] Y. J. Yoon**, M. S. Cho, B. G. Kim, J. H. Seo, and I. M. Kang*, "Capacitorless One-Transistor Dynamic Random-Access Memory Based on Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor with Si/SiGe Heterojunction and Underlap Structure for Improvement of Sensing Margin and Retention Time" Journal of Nanoscience and Nanotechnology 19, 6023.
[19] W. D. Jang**, Y. J. Yoon, M. S. Cho, J. H. Jung, S. H. Lee, J. Jang, J.-H. Bae, and I. M. Kang*, "Design and Optimization of Germanium-Based Gate-Metal-Core Vertical Nanowire Tunnel FET" Micromachines 10, 749.
[18] Y. J. Yoon**, J. H. Seo**, S. Cho, J.-H. Lee, and I. M. Kang*, "A polycrystalline-silicon dual-gate MOSFET-based 1T-DRAM using grain boundary-induced variable resistance" Applied Physics Letters 144, 183503.
[17] J. H. Seo**, Y. J. Yoon**, E. Yu, W. Sun, H. Shin, I. M. Kang, J.-H Lee*, and S. Cho*, "Fabrication and Characterization of a Thin-Body Poly-Si 1T DRAM With Charge-Trap Effect" IEEE Electron Device Letters 40, 566.
[16] Q. Dai**, D.-H. Son, Y.-J. Yoon, J.-G. Kim, X. Jin, I.-M. Kang, D.-H. Kim, Y. Xu, S. Cristoloveanu, and J.-H Lee*, "Deep Sub-60 mV/decade Subthreshold Swing in AlGaN/GaN FinMISHFETs with M-Plane Sidewall Channel" IEEE Transactions on Electron Devices 66, 1699.
2018
[15] Y. J. Yoon**, J. H. Seo, and I. M. Kang*, "Capacitorless one-transistor dynamic random access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure" Japanese Journal of Applied Physics 57, 04FG03.
2017
[14] Y. J. Yoon**, J. H. Seo, M. S. Cho, B. G. Kim, S. H. Lee, and I. M. Kang*, "Capacitorless one-transistor dynamic random access memory based on double-gate GaAs junctionless transistor" Japanese Journal of Applied Physics 56, 06GF01.
2016
[13] Y. J. Yoon**, J. H. Seo, M. S. Cho, H.-S. Kang, C.-H. Won, I. M. Kang*, and J.-H. Lee*, "TMAH-based wet surface pre-treatment for reduction of leakage current in AlGaN/GaN MIS-HEMTs" Solid-State Electronics 124, 54. Editor's Choice Selection
2015
[12] Y. J. Yoon**, H. R. Eun, J. H. Seo, H.-S. Kang, S. M. Lee, J. Lee, S. Cho*, H.-S. Tae, J.-H. Lee, and I. M. Kang*, "Short-Channel Tunneling Field-Effect Transistor with Drain-Overlap and Dual-Metal Gate Structure for Low-Power and High-Speed Operations" Journal of Nanoscience and Nanotechnology 15, 7430.
[11] J. H. Seo**, Y. J. Yoon, S. Lee, J.-H. Lee, S. Cho*, and I. M. Kang*, "Design and analysis of Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET)" Current Applied Physics 15, 208.
2014
[10] H.-S. Kang**, D.-S. Kim, C.-H. Won, Y.-J. Kim, Y. J. Yoon, D-K. Kim, J.-H. Lee, Y. H. Bae, and S. Cristoloveanu, "Impact of Multi-Layer Carbon-Doped/Undoped GaN Buffer on Suppression of Current Collapse in AlGaN/GaN HFETs" International Journal of High Speed Electronics and Systems 23, 1450017.
[9] Y. J. Yoon**, H.-S. Kang, J. H. Seo, Y.-J. Kim, J.-H. Bae, J.-H. Lee, S. Cho, E.-S. Cho, and I. M. Kang*, "Design of a Recessed-gate GaN-based MOSFET Using a Dual Gate Dielectric for High-power Applications" Journal of the Korea Physical Society 65, 1579.
[8] H. R. Eun**, S. Y. Woo, H. G. Lee, Y. J. Yoon, J. H. Seo, J.-H. Lee, J. Kim, and I. M. Kang*, "Investigation of InAs/InGaAs/InP Heterojunction Tunneling Field-Effect Transistors" Journal of Electrical Engineering & Technology 9, 1654.
[7] S. Y. Woo**, Y. J. Yoon, J. H. Seo, G. M. Yoo, S. Cho*, and I. M. Kang*, "InGaAs/Si Heterojunction Tunneling Field-Effect Transistor on Silicon Substrate" IEICE Transactions on Electronics E97-C, 677.
[6] Y. J. Yoon**, J. H. Seo, H.-S. Kang, Y.-J. Kim, J.-H. Bae, E.-S. Cho, J.-H. Lee, S. Cho*, and I. M. Kang*, "Effect of spacer dielectrics on performance characteristics of Ge-based tunneling field-effect transistor" Japanese Journal of Applied Physics 53, 06JE05.
[5] Y. J. Yoon**, J. H. Seo, E.-S. Cho, J.-H. Lee, J.-H. Bae, S. Cho, and I. M. Kang*, "Heteromaterial Gate Tunneling Field-Effect Transistor for High-Speed and Radio-Frequency Applications" Journals of Nanoscience and Nanotechnology 14, 8136.
2013
[4] S. Y. Woo**, Y. J. Yoon, S. Cho, J.-H. Lee, and I. M. Kang*, "Analysis on RF Parameters of Nanoscale Tunneling Field-Effect Transistor Based on InAs/InGaAs/InP heterojunctions" Journals of Nanoscience and Nanotechnology 13, 8133.
[3] K. R. Kim**, Y. J. Yoon*, S. Cho, J. H. Seo, J.-H. Lee, J.-H. Bae, E.-S. Cho, and I. M. Kang*, "InGaAs/InP heterojunction-channel tunneling field-effect transistor for ultra-low operation and standby power application below supply voltage of 0.5 V" Current Applied Physics 13, 2051.
[2] Y. J. Yoon**, S. Cho*, J. H. Seo, I. M. Kang*, B.-G. Park, and J.-H. Lee, "Compound Semiconductor Tunneling Field-Effect Transistor Based on Ge/GaAs Heterojunction with Tunneling-Boost Layer for High-Performance Operation" Japanese Journal of Applied Physics 52, 04CC04.
2012
[1] Y. J. Yoon**, S. Y. Woo, J. H. Seo, J. S. Lee, Y. S. Park, J.-H. Lee, and I. M. Kang*, "Design Optimization of Vertical Double-gate Tunneling Field-effect Transistors" Journal of the Korea Physical Society 61, 1679.