2024

• Bandwidth-Effective DRAM Cache for GPUs with Storage-Class Memory
  Jeongmin Hong, Sungjun Cho, Geonwoo Park, Wonhyuk Yang, Young-Ho Gong, and Gwangsun Kim
  IEEE International Symposium on High-Performance Computer Architecture (HPCA), Edinburgh, UK, March 2024. (BK21+ SCIE IF: 4) 

2023

• HedgeRank: Heterogeneity-Aware, Energy-Efficient Partitioning of Personalized PageRank at the Edge
  Young-Ho Gong*
  Micromachines, 14(9), 1714, August 2023. (SCIE IF: 3.4)

• Twin ECC: A Data Duplication Based ECC for Strong DRAM Error Resilience
  Hyeong Kon Bae, Myung Jae Chung, Young-Ho Gong*, and Sung Woo Chung*
  Design, Automation and Test in Europe Conference (DATE), Antwerp, Belgium, April 2023. (BK21+ SCIE IF: 2) 

• Scale-CIM: Precision-Scalable Computing-in-Memory for Energy-Efficient Quantized Neural Networks
  Young Seo Lee, Young-Ho Gong*, and Sung Woo Chung*
  Journal of Systems Architecture, vol. 134, January 2023. (SCIE IF: 5.836, Top 10.9% in JCR 2021)

2022

• A Layer-Wise Frequency Scaling for a Neural Processing Unit
  Jaehoon Chung, HyunMi Kim, Kyoungseon Shin, Chun-Gi Lyuh, Yong Cheol Peter Cho, Jinho Han, Youngsu Kwon, Young-Ho Gong*, and Sung Woo Chung*
  ETRI Journal, vol. 44, no. 5, pp. 849-858, October 2022. (SCIE IF: 1.347)

• Stealth ECC: A Data-Width Aware Adaptive ECC Scheme for DRAM Error Resilience
  Young Seo Lee, Gun Jae Koo, Young-Ho Gong*, and Sung Woo Chung*
  Design, Automation and Test in Europe Conference (DATE), Antwerp, Belgium, March 2022. (BK21+ SCIE IF: 2) 

2021

• Quant-PIM: An Energy-efficient Processing-in-memory Accelerator for Layer-wise Quantized Neural Networks
  Young Seo Lee, Eui-Young Chung, Young-Ho Gong*, and Sung Woo Chung*
  IEEE Embedded Systems Letters (ESL), vol.13, no.4, pp.162-165, December 2021. (SCIE IF: 1.524)

• Characterizing the Thermal Feasibility of Monolithic 3D Microprocessors
  Ji Heon Lee, Young Seo Lee, Jeong Hwan Choi, Hussam Amrouch, Joonho Kong, Young-Ho Gong*, and Sung Woo Chung*
  IEEE Access, vol. 9, pp. 120715-120729, August 2021. (SCIE IF: 3.367)

• Quantifying the Impact of Monolithic 3D (M3D) Integration on L1 Caches
  Young-Ho Gong, Joonho Kong, and Sung Woo Chung
  IEEE Transactions on Emerging Topics in Computing (TETC), vol. 9, no. 2, pp. 854-865, April-June 2021.
  (SCIE IF: 6.595, Top 6.8% in JCR 2020).

• A System-level Exploration of Binary Neural Network Accelerators with Monolithic 3D based Compute-in-Memory SRAM
  Jeong Hwan Choi, Young-Ho Gong*, and Sung Woo Chung*
  Electronics, 10(5), 623, March 2021. (SCIE IF: 2.397)

• Monolithic 3D-based SRAM/MRAM Hybrid Memory for an Energy-efficient Unified L2 TLB-Cache Architecture
  Young-Ho Gong*
  IEEE Access, vol. 9, pp. 18915-18926, January 2021. (SCIE IF: 3.367)

• Monolithic 3D Stacked Multiply-Accumulate Units
  Young Seo Lee, Kyung Min Kim, Ji Heon Lee, Young-Ho Gong, Seon Wook Kim, and Sung Woo Chung*
  Integration, the VLSI journal, vol. 76, pp. 183-189, January 2021. (SCIE IF: 1.211)

2019

• Exploring the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling Efficiency
  Cong Thuan Do, Young-Ho Gong, Cheol Hong Kim, Seon Wook Kim, and Sung Woo Chung
  IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Lausanne, Switzerland, July 2019. (BK21+ SCIE IF: 1)

• A High Speed Multiply-Accumulate (MAC) Unit: Case Studies on 3D Stacked FPGA and ASIC
  Young Seo Lee, Kyung Min Kim, Sang Jun Nam, Young-Ho Gong, Seon Wook Kim, and Sung Woo Chung
  Design Automation Conference (DAC), Las Vegas, USA, June 2019. (poster presented in WIP (Work-in-Progress) session)

2018

• Thermal Modeling and Validation of a Real-World Mobile AP
  Young-Ho Gong, Jae Jeong Yoo, and Sung Woo Chung
  IEEE Design & Test (D&T), vol. 35, no. 1, pp. 55-62, February 2018. (SCIE IF: 2.409)

• Thermal Modeling and Validation of a Real-World Mobile AP
  Young-Ho Gong, Jae Jeong Yoo, and Sung Woo Chung
  IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, May 2018.
  (This summary paper (originally published in IEEE Design and Test) was presented in TCAS session.)

~2017

• An Efficient Trade-Off between Yield and Energy for eDRAM Caches under Process Variations
  Joonho Kong and Young-Ho Gong
  Microprocessors & Microsystems (MICPRO), vol. 55, November 2017. (SCIE IF:1.161)

• Architecting Large-Scale SRAM Arrays with Monolithic 3D Integration
  Joonho Kong, Young-Ho Gong, and Sung Woo Chung
  IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Taipei, Taiwan, July 2017. (BK21+ SCIE IF: 1)

• Towards Refresh-optimized EDRAM-based Caches with a Selective Fine-grain Round-robin Refresh Scheme
  Joonho Kong, Young-Ho Gong, and Sung Woo Chung
  Microprocessors and Microsystems (MICPRO), vol. 49, pp. 95-104, March 2017. (SCIE IF: 1.161)

• Exploiting Refresh Effect of DRAM Read Operations: A Practical Approach to Low-power Refresh
  Young-Ho Gong and Sung Woo Chung
  IEEE Transactions on Computers (TC), vol. 65, no. 5, pp. 1507-1517, May 2016. (SCIE IF: 2.711)

• Exploration of Temperature-aware Refresh Schemes for 3D Stacked eDRAM Caches
  Young-Ho Gong, Jae Min Kim, Sung Kyu Lim, and Sung Woo Chung
  Microprocessors and Microsystems (MICPRO), vol. 42, pp. 100-112, May 2016. (SCIE IF: 1.161)

• Performance and Cache Access Time of SRAM-eDRAM Hybrid Caches Considering Wire Delay
  Young-Ho Gong, Hyung Beom Jang, and Sung Woo Chung
  International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, March 2013.