Verification of a 64-bit RSA Encryption Engine using UVM

This project was done in partial fulfillment of the requirements for the Master's degree in Electrical and Computer Engineering. It was completed at San Francisco State University in December 2024. 

This project involves verifying the design of a 64-bit RSA encryption engine using the Universal Verification Methodology (UVM) to create a detailed testbench. The design under test (DUT) is based on a Verilog implementation of RSA by Rehan Shams, Fozia Hanif Khan, and Mohammad Umair, aimed at developing a standard FPGA-based secure communication device. The report explores UVM, its components, and their roles in verification, as well as the RSA encryption method’s history, principles, and applications. The core focus is the creation of a UVM testbench, with explanations of its implementation and effectiveness demonstrated through simulation results and coverage metrics. The work underscores UVM’s importance in verifying cryptographic hardware and RSA's relevance in modern security.