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Wafer-Scale Computing for HPC:
Overview
Overview
Presentation slide is now available, HERE (2026-01-30)
Wafer-Scale Computing (WSC) is attracting increasing attention, but its significant differences from conventional computing architectures keep the barrier to entry high.
This BoF aims to provide a concise overview of the current state and challenges of WSC, identify its applicability to general-purpose computing, and outline concrete directions for future research.
The session will also place particular emphasis on community building and on creating opportunities for future collaboration.
Using the Cerebras CS series as a concrete example, the BoF will ground the practice conversation, remain non-commercial, and foster open discussion.
Timeline
Timeline
1. 0:00 – 0:05 Opening (5 minutes)
- Greeting and purpose of the BoF
2. 0:05 – 0:25 Self-introductions + Research Topics (25 minutes total)
- Each speaker: Name, affiliation, current research topic, and relationship to WSC
- About 5–6 minutes per speaker for four speakers
3. 0:30 – 0:50 Panel Discussion (20 minutes)
- Moderator presents discussion points; panelists discuss and take Q&A from the audience
- Discussion
4. 0:50 – 0:55 Community Building (5 minutes)
- Confirm shared platform proposal, initial deliverables (mini-benchmarks / datasets, etc.), and contact/participation methods
5. 0:55 – 1:00 Wrap-up (5 minutes)
- Summary of outcomes
Speakers
Speakers
Michael James (Cerebras)
Kazutomo Yoshii (Argonne National Laboratory)
Robert Underwood (Argonne National Laboratory)
Acknowledgement
Acknowledgement
This work was supported by Japan Science and Technology Agency (JST) as part of Adopting Sustainable Partnerships for Innovative Research Ecosystem (ASPIRE), Grant Number JPMJAP2341. This work was supported by JSPS KAKENHI Grant Number 24K14972. This work was supported by MEXT Feasibility Study on the future HPCI.
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