SPEAKERS

ABSTRACT

Placement and routing are the most time-consuming steps in the FPGA physical design flow. We show that switching from a net-based to a connection-based heuristic resulted in Liquid and CRoute, our open source placement and routing solutions for FPGA design. These are much faster than previous tools with similar total wirelength and critical path results. CRoute has also been integrated into AMD/Xilinx’ Rapidwright framework and is offered by AMD/Xilinx as RWRoute. We are currently extending both Liquid and CRoute to multi-die versions MDLiquid and MDroute. We present the first results on these new tools.

SHORT BIO 

Prof. Stroobandt received the M.S. degree (1994) and Ph.D. degree (1998) in electrical engineering from Ghent University in Belgium and he is a professor there since 2002. He was co-founder in 1999 of the System-Level Interconnect Prediction (SLIP) workshop and has been involved in many editions of the Workshop on Reconfigurable Computing at HiPEAC. He has always had a keen interest in interconnect-related research and its applications in physical design tools for FPGA’s. His current focus is in placement and routing algorithms for FPGA’s, moving into logic synthesis.

ABSTRACT

High-Level Synthesis (HLS) tools enable programmers to automatically generate hardware designs from high-level software abstractions instead of writing tedious and time-consuming low-level hardware descriptions. However, today’s HLS tools are still accessible only to expert users and for particular classes of applications; generating good-quality circuits still requires peculiar code restructuring and extensive experimentation with the tools. In this talk, I will discuss the challenges and limitations of current HLS approaches. I will outline an alternative HLS technique that overcomes these limitations and achieves high parallelism in general-purpose software applications. Finally, I will share my vision of future advancements in HLS and discuss the role of HLS in designing next-generation hardware applications.

SHORT BIO 

Lana Josipović is an Assistant Professor in the Department of Information Technology and Electrical Engineering at ETH Zurich. Prior to joining ETH Zurich in January 2022, she received a Ph.D. degree in Computer Science from EPFL, Switzerland. Her research interests include reconfigurable computing and electronic design automation, with an emphasis on high-level synthesis techniques to generate hardware designs from high-level programming languages. She developed Dynamatic, an open-source high-level synthesis tool that produces dynamically scheduled circuits from C/C++ code. She is a recipient of the EDAA Outstanding Dissertation Award, Google Ph.D. Fellowship in Systems and Networking, Google Women Techmakers Scholarship, and Best Paper Award at FPGA'20.

ABSTRACT

State-of-the-art Artificial Intelligence complexity has grown exponentially in recent years, leading to the adoption of programmable-based hardware accelerators to face the computational power required by the new computing architecture. The reliability evaluation of the hardware accelerator is still premature and requires suitable methods to measure the safety standards required by mission-critical applications. The possibility to adapt the hardware accelerator size and performance to different computational needs enhanced the interest of safety-critical applications such as automotive and avionics. For this reason, the interest in studying the reliability of hardware accelerators used in artificial intelligence platforms is growing. In this presentation, we provide an overview of the recent approaches for evaluating the resiliency of hardware accelerators when implemented on FPGA architecture devoted to Artificial Intelligence platforms. Experimental results are commented on taking into account the insight into the hardware-level architectures implemented on FPGAs with three types of configuration memory: Flash-based, SRAM-based and Radiation-Hardened.

SHORT BIO 

Prof. Luca Sterpone took his MS and PhD degrees from Politecnico di Torino; he is now a Full Professor and Director of the Department of Control and Computer Engineering of the same institution. He coordinates the Aerospace and Safety Computing Laboratory (ASAC). He is the author of more than 230 papers and he received several awards for his research activity such as the Best Paper award at the IEEE European Test Symposium (2005) and the EDAA Outstanding Dissertation Award in 2007, the Best Tool Award at the IEEE Conference on Synthesis, Modeling, Analysis and Simulation Methods (SMACD 2018). He has been General Chair and Program Co-chair of HiPEAC Reconfigurable Computing Workshop (2013 and 2013). He has been General Chair of ACM International Symposium on Computing Frontiers and he is General Chair of 34rd IEEE International Conference on Field-Programmable Logic and Applications (FPL 2024). He is an expert for the European Health and Digital Executive Agency (HaDEA) and he served as evaluator for the European Commission (EC) for the Horizon Europe and Horizon 2020 Programs: FET HPC, ICT, Project Monitoring and EURO-HPC.

ABSTRACT

Designing runtime adaptive hardware accelerators for FPGAs is still a cumbersome process. The standard design process still requires complete hardware accelerators to be synthesized at design time for dynamic instantiation at run time. However, this only allows you to support application scenarios that are known at design time, limiting runtime adaptability. We address these limitations by providing a flexible and scalable architectural template for designing domain-specific FPGA overlays. The template can be parameterized in terms of number and size of tiles, communication topology, and connectivity to external RAM. The tiles consist of configurable routing resources and the actual processing kernels, which are exchanged at runtime through dynamic partial reconfiguration. To simplify kernel design, all interfaces are AXI stream compliant. This enables scenarios where a fixed domain-specific overlay is quickly deployed on an FPGA, and at runtime, varying dataflow graphs are executed by loading pre-synthesized kernels into adjacent tiles. Using this template, the task of implementing a data flow processing overlay for any application domain is transformed from extensive development work to straightforward parameterization and deployment. We demonstrate this by constructing an overlay for analytical database query processing based on the proposed template.

SHORT BIO 

Thilo Pionteck is professor for Hardware-Oriented Technical Computer Science at the Faculty of Electrical Engineering and Information Technology at the Otto-von-Guericke University Magdeburg, Germany. He received his Ph.D. in Electrical Engineering from the Technical University of Damstadt in 2005. He then joined the University of Lübeck as a postdoc and later as an assistant professor. From 2012 to 2014, he was the substitute of the Chair of Embedded Systems at the Technische Universität Dresden, and the Chair of Computer Engineering at the Technische Universität Hamburg Harburg. In 2015, he was appointed as professor at the Chair of Organic Computing at the University of Lübeck, before he moved to Magdeburg in 2016. His research interests include the design of runtime adaptive hardware accelerators, on-chip communication architectures, heterogeneous 3D SoC designs, methodologies for systematic design space exploration, and runtime management of heterogeneous system architectures.

ABSTRACT

At RIKEN Center for Computational Science (R-CCS), we have been developing an experimental FPGA Cluster named "ESSPER (Elastic and Scalable System for high-PErformance Reconfigurable computing)," which is a research platform for reconfigurable HPC. ESSPER is composed of sixteen Intel Stratix 10 SX FPGAs which are connected to each other by a dedicated 100Gbps inter-FPGA network. We have developed our own Shell (SoC) and its software APIs for the FPGAs supporting inter-FPGA communication. ESSPER is connected to Supercomputer Fugaku which is deployed in RIKEN, so that we can experimentally use FPGAs in ESSPER on computing nodes of Fugaku with the software bridged Intel's OPAE FPGA driver, called Remote-OPAE. In this talk, I introduce ESSPER's concept, designed system stack with hardware and software, and lessons we learned as issues of FPGA-based HPC. I also talk about our recent research activity on coarse-grained reconfigurable array (CGRA) as another reconfigurable architecture to address the issues as well as our future prospects for reconfigurable HPC in the future.

SHORT BIO 

Kentaro Sano is the team leader of the processor research team at RIKEN Center for Computational Science (R-CCS) since 2017, responsible for research and development of future high-performance processors and systems. He is also a visiting professor with an advanced computing system laboratory at Tohoku University. He received his Ph.D. from the graduate school of information sciences, Tohoku University, in 2000. From 2000 until 2018, he was a Research Associate and an Associate Professor at Tohoku University. He was a visiting researcher at the Department of Computing, Imperial College, London, and Maxeler Technology corporation in 2006 and 2007. His research interests include data-driven and spatial-parallel processor architectures such as a coarse-grain reconfigurable array (CGRA), FPGA-based high-performance reconfigurable computing, high-level synthesis compilers and tools for reconfigurable custom computing machines, and system architectures for next-generation supercomputing based on the data-flow computing model.

ABSTRACT

Customizing reconfigurable accelerators for a given application and a computational platform remains a challenge. In this talk we will address the challenges along the three main dimensions for optimization; i.e., the area (the Space), the computational precision (the Value) and the throughput/latency (the Time) of reconfigurable accelerators. Some examples based on FPGA based accelerators will be provided, however, the techniques discussed are applicable to other systems with reconfigurable computational substrates.

SHORT BIO 

Georgi Gaydadjiev is a computer engineer with more than 35 years of experience in the Industry and Academia. He contributed to the development of a wide range of computer systems; from small, battery-operated devices up to application-specific supercomputers. Currently he holds the Chair Professor in Computer Architecture at the Delft University of Technology and is also honorary visiting professor at the Department of Computing of Imperial College London since 2014. Previously, he held the Chair in Innovative Computer Architectures at the University of Groningen till June 2023, and was a Chair in Computer Systems Engineering at Chalmers University of Technology in Sweden until May 2015. Georgi’s work received several recognitions, including the Design & Engineering Showcase Award at the Consumer Electronics Show (CES 1999) and the best papers from the 24th International Conference on Supercomputing (ICS'10) and USENIX/SAGE Large Installation System Administration conference (LISA 2006). Georgi remains a member of the CogniGron program board and is currently advising several high-tech companies. His research interests include, among others, application and data centric computer systems design, advanced computer architecture and micro-architecture, reconfigurable computing, hardware/software co-design, and Embedded Systems design.