Research Projects
Research Projects
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High Efficiency Cross-Correlation using Level-Crossing ADC
High Efficiency Cross-Correlation using Level-Crossing ADC
A level-crossing ADC to achieve feature signal recognition at low power consumption. This strategy leverages asynchronous circuitry to detect incoming pulse shape without high-frequency digital electronics.
Developed a 64-tap FIR filter and peripheral digital units in Cadence in the TSMC 40 nm process with 37 ps resolution and 5 ns max tap delay.
Executed schematic and simulation for the delay chain, shift register, pulse width normalizer, and logic unite.
Conducted layout of the FIR filter in a 225 × 1120 um area, integrating post-layout Monte-Carlo simulation.
Assembled testing board and conducted chip characterization; constructed FPGA test bench in VHDL.
CMOS Imager with Adjustable Local Resolution
CMOS Imager with Adjustable Local Resolution
An imager that can locally adjust its resolution in the desired area to minimize data throughput, power consumption, and subsequent image processing workload. The resolution turning is achieved through grouping neighboring pixels. The imager is freely programable and an external algorithm can be used for control.
Conceptualized and validated a CMOS image sensor, empowering localized resolution adjustability to reduce any amount of post data processing load per application needs.
Architected the image sensor system, performed algorithm verification and functionality testing in MATLAB.
Schemed transistor level circuits on Cadence, including photodiode activation latches, a 96 × 96 pixels array, decoders, CTIA, and the current-to-frequency converter.
Simulated and optimized schematic; conducted layout in a 2 × 2 mm area for post-layout simulation.
Neural Network Composed of Multi-Input Transistor
Neural Network Composed of Multi-Input Transistor
An artificial synapse structure based on a eutectogel multi-gating transistor. Multiple gates are fabricated onto one transistor to achieve multiple inputs. The effective gate voltage of the transistor is a weighted sum of all gate inputs. The system is designed in the shape of a 2D plain, with four gates on the corners of the square. The transistor channel can be placed on any location on the plain and the distance from the channel to each gate determines the corresponding weight.
Engineered and executed experiments to analyze a novel multi-input transistor topology, showcasing the ability to perform matrix multiplication and neuron network through device physics.
Conducted device modeling of multi-input transistors in LTSPICE; acquired characterization data through experiment and utilized MATLAB for data fitting to improve model accuracy.
Designed a pulse-width modulated charge-and-fire neuron network using the created model in simulation.
Built 3D models for molding the device in SolidWorks, and 3D-printed the parts for device fabrication.
Thread-Based Electro-Chemical Transistor & Circuit
Thread-Based Electro-Chemical Transistor & Circuit
A complex three-dimensional integrated circuit on single thread achieves ultimate flexibility and utilizes non-volatile breathable gels for transistor action. The organic transistor, as well as resistor, diode, and other electrical components are fabricated in the form of a single thread to form a complex analog circuit. Designed single-stage and two-stage amplifiers work at 1.5 V and achieved a gain of 3.2 V/V and 34 V/V, respectively. Integrated with a thread-based strain sensor, the circuit sucessfully monitors eye blinking and respiration.
Orchestrated collaboration with chemical engineers to pioneer the fabrication of wearable thread transistors and circuits; led experiment to characterize transistor parameters using oscilloscope, function generator, etc.
Created a mathematical-physical model for the transistor based on characterized data in LTSPICE; performed simulations to design complicated circuit such as voltage doubler and charge-and-fire neuron.
Implemented single-stage and two-stage amplifiers in actual device, with a gain of 3.2 and 34 V/V, respectively.
Prototyped a wearable thread device that captured eye blinking and respiration to demonstrate real-time health monitoring application.
Wearable System for Bio-Signal Monitoring with Dry Electrodes
Wearable System for Bio-Signal Monitoring with Dry Electrodes
A smart bodysuit and eye-mask system to monitor electrical bio-signals, including ECG, EMG, EOG, and body positioning. A gold-coated nanomesh is used as the dry electrode to achieve long-term comfort and functionality. Multi-channel signals are processed and transmitted by one set of electronics that is fixed on the bodysuit for maximized wearability.
Fabricated and optimized a gold nanomesh using electrospinning technique and e-beam evaporation. The nanomesh adheres to skin texture, and functions as contacts between human skin and electronics.
Proposed bio-signals were captured with participants in the laboratory settings
Zero-Power Shape Morphing Antenna
Zero-Power Shape Morphing Antenna
A series of antennas made with shape memory alloy (SMA). The antenna changes shape according to the temperature it experiences, and thus alters its properties accordingly. Leveraging the hysteresis of the heating and cooling process, the antenna can be designed to record history information without electrical power.
Manufactured history temperature extrema sensing antennas from two-way Shape Memory Alloy. The antenna changes configuration without external power, but is controlled by the temperature extremes it experiences.
Performed simulations of the antenna in HFSS. Optimized antenna parameters based on the results.
Fabricated the antenna and characterized the return loss using a VNA at various conditions.
Depending on the focus of the application, altering different parameters of the antenna was achieved, including radiation pattern, frequency, and input impedance.
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