期刊論文
1995
Shen-Fu Hsiao and Jean-Marc Delosme, “Householder CORDIC Algorithms,” IEEE Trans. on Computers, Vol. 44, No. 8, pp. 990-1001, Aug. 1995.
1996
Shen-Fu Hsiao and Jean-Marc Delosme, “Parallel Singular Value Decomposition of Complex Matrices Using Multidimensional CORDIC Algorithms,” IEEE Trans. on Signal Processing, Vol. 44. No. 3, pp. 685-697, Mar. 1996.
1997
Chungnan Lee, Tony-yee Lee, Shen-Fu Hsiao and Tain-chi Lu, “Performance Studies for Selected Applications on a Network of Workstations,” Journal of High Performance Computing, Vol.4, No. 1, pp. 25-35, Dec. 1997.
1998
Shen-Fu Hsiao, “VLSI Implementation of the Quadratic-Spline W-Transform for Multi-resolution Image Processing,” IEE Electronics Letters, Vol. 34, No. 3, pp. 258-259, Feb. 1998.
Shen-Fu Hsiao, Ming-Roun Jiang, and Jia-Sien Yeh, “Design of High-Speed Low-Power 3-2 Counter and 4-2 Compressor for Fast Multipliers,” IEE Electronics Letters, Vol. 34, No. 4, pp. 341-343, Feb. 1998.
Shen-Fu Hsiao and Jia-Siang Yeh, “Top-Down Logic Design with Pass-Transistor Cells And an Efficient Synthesizer,” IEE Electronics Letters, Vol. 34, No. 12, pp. 1180-1182, June 1998.
Shen-Fu Hsiao, Wen-Chen Huang, Chungnan Lee, and Cheng-Chung Hsu,“A Hybrid W-Transform-Based Coding and Its VLSI Realization for Image Compression,” IEEE Trans. on Consumer Electronics, Vol. 44, No. 3, pp. 509-518, Aug. 1998.
Shen-Fu Hsiao and Jen-Yin Chen, “Design, Implementation and Analysis of a New Redundant CORDIC Processor with Constant Scaling Factor and Regular Structure,” Journal of VLSI Signal Processing, Vol. 20, No. 3, pp. 267-278, Dec. 1998.
1999
Shen-Fu Hsiao, Wei-Ren Shiue, and Jian-Ming Tseng, “A Cost-Efficient and Fully-Pipelinable Linear Architecture for Discrete Cosine Transform,” IEEE Trans. on Consumer Electronics, Vol.45, No.3, pp. 515-525, Aug. 1999.
2000
Shen-Fu Hsiao and Ming-Rong Jiang, “An Efficient Synthesizer for Generation of Fast Parallel Multipliers,” IEE Proc. Computers and Digital Techniques, Vol. 147, No. 1, pp. 49-52, Jan. 2000.
Shen-Fu Hsiao, Chun-Yi Lau, and Jean-Marc Delosme, “Redundant Constant-Factor Implementation of Multi-dimensional CORDIC and Its Application to Complex SVD,” Journal of VLSI Signal Processing, Vol. 25, No. 2, pp. 155-166, June 2000.
Shen-Fu Hsiao and Chun-Yi Lau, “Design of a Unified Arithmetic Processor Based on Redundant Constant-Factor CORDIC with Merged Scaling Operation,” IEE Proc. Computers and Digital Techniques, Vol. 147, No. 4, pp. 297-303, July 2000.
Shen-Fu Hsiao, Yor-Chin Tai, and Kai-Hsiang Chang, “VLSI Design of an Efficient Embedded Zerotree Wavelet Coder with Function of Digital Watermarking,” IEEE Trans. on Consumer Electronics, Vol. 46, No. 3, pp. 628-636, Aug. 2000.
Shen-Fu Hsiao, Wei-Ren Shiue, and Jian-Ming Tseng, “Design and Implementation of a Novel Linear-Array DCT/IDCT Processor with Complexity of Order logN,” IEE Proc. Vision, Image, and Signal Processing, Vol. 147, No. 5, pp. 400-408, Oct. 2000.
Shen-Fu Hsiao and Wei-Ren Shiue, “Design of Low-Cost and High-Throughput Linear Arrays for DFT Computations: Algorithms, Architectures and Implementations,” IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 47, No. 11, pp. 1188-1203, Nov. 2000.
2001
Shen-Fu Hsiao and Jia-Ming Tseng, “Parallel, Pipelined and Folded Architectures for Computation of 1-D and 2-D DCT in Image and Video Coding,” Journal of VLSI Signal Processing, Vol. 28, No. 3, pp. 205-220, July 2001.
Shen-Fu Hsiao and Wei-Ren Shiue, “A New Hardware-Efficient Algorithm and Architecture for Computation of 2-D DCT on a Linear Systolic Array,” IEEE Trans on Circuits and Systems for Video Technology, Vol. 11, No. 11, pp. 1149-1159, Nov. 2001.
2002
Shen-Fu Hsiao and Jian-Ming Tseng, “New Matrix Formulation for Two-Dimensional DCT/IDCT Computation and Its Distributed-Memory VLSI Implementation,” IEE Proc. Vision, Image and Signal Processing, Vol. 149, No. 2, pp. 97-107, Apr. 2002.
Shen-Fu Hsiao, Jia-Siang Yeh and Da-Yen Chen, “High-Performance Multiplexer-Based Logic Synthesis Using Pass-Transistor Logic,” VLSI Design, Vol. 15, No. 1, pp. 417-426, Aug. 2002.
2004
Shen-Fu Hsiao, Yu-Hen Hu, and Tso-Bing Juang, “A Memory-Efficient and High-Speed Sine/Cosine Generator Based on Parallel CORDIC Rotations,” IEEE Signal Processing Letters, Vol. 11, No. 2, pp. 152-155, Feb. 2004.
Tso-Bing Juang, Shen-Fu Hsiao, and Ming-Yu Tsai, “Para-CORDIC: Parallel CORDIC Rotation Algorithm,” IEEE Trans. on Circuits and Systems, I: Regular Papers, Vol. 51, No. 8, pp. 1515-1524, Aug. 2004.
2005
Tso-Bing Juang and Shen-Fu Hsiao, “Low-Error Carry-Free Fixed-Width Multipliers with Low-Cost Compensation Circuits,” IEEE Trans. on Circuits and Systems, Part-II, Vol. 52, No. 6, pp. 299-303, June 2005.
Tso-Bing Juang, Shen-Fu Hsiao, Ming-Yu Tsai, and Jeng-Hsiung Jan, “A Cell-Driven Multiplier Generator with Delay Optimization of Partial Products Compression and an Efficient Partition Technique for the Final Addition,” IEICE Transactions on Information and Systems, Vol.E88-D No.7 pp.1464-1471, July 2005.
Shen-Fu Hsiao, Yu Hen Hu, Tso-Bing Juang, and Chung-Han Lee, “Efficient VLSI Implementations of Fast Multiplierless Approximated DCT using Parameterized Hardware Modules,” IEEE Trans. Circuits and Systems, Part-I: Regular Papers, Vol. 52, No. 8, pp. 1568-1579, Aug. 2005.
Shen-Fu Hsiao and Ming-Chih Chen, “Efficient Substructure Sharing Methods for Optimizing the Inner-Product Operations in Rijndael Advanced Encryption Standard,” IEE Proc. Computers and Digital Techniques, Vol. 152, No. 5, pp. 653-665, Sept. 2005.
Shen-Fu Hsiao, Ming-Chih Chen, Ming-Yu Tsai, and Chi-Chen Lin, “System-on-Chip Implementation of the Whole Advanced Encryption Standard (AES) Processor Using Reduced XOR-based Sum-of-Product Operations,” IEE Proc. Information Security, Vol. 152, No. 1, pp. 21-30, Oct. 2005.
2006
Shen-Fu Hsiao, Ming-Chih Chen and Chia-Shin Tu, “Memory-Free Low-Cost Designs of Advanced Encryption Standard Using Common Subexpression Elimination for Sub-functions in Transformations,” IEEE Trans. Circuits and Systems, Part I: Regular Papers, Vol. 53, No. 3, pp. 615-626, Mar. 2006.
2009
Ming-Chih Chen and Shen-Fu Hsiao, “Low Cost Design of an Advanced Encryption Standard (AES) Processor Using a New Common-Subexpression-Elimination Algorithm,” IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, Vol.E92-A, no.12, pp. 3221-3228, Dec. 2009.
2010
Shen-Fu Hsiao, Ming-Yu Tsai, and Chia-Sheng Wen, “Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment,” IEEE Trans. Circuits and Systems, Part-II, vol. 57, no. 1, pp. 21-25, Jan. 2010.
2011
Hou-Jen Ko and Shen-Fu Hsiao, “Design and Application of Faithfully Rounded and Truncated Multipliers with Combined Deletion, Reduction, Truncation, and Rounding,” IEEE Trans. Circuits and Systems, Part-II, vol. 58, no. 5, pp. 304-308, May 2011.
2012
Shen-Fu Hsiao, Hou-Jen Ko, and Chia-Sheng Wen, “Two-Level Hardware Function Evaluation Based on Correction of Normalized Piecewise Difference Functions,” IEEE Trans. Circuits and Systems, Part-II, vol. 59, no. 5, pp. 292-296, May 2012.
2013
Shen-Fu Hsiao, Hou-Jen Ko, Yu-Ling Tseng, Wen-Liang Huang, Shin-Hung Lin, and Chia-Sheng Wen, “Design of Hardware Function Evaluators Using Low-Overhead Non-uniform Segmentation with Addressing Remapping,” IEEE Trans. VLSI Systems, vol. 21, no. 5, pp. 875-886, May 2013.
Shen-Fu Hsiao, Jun-Hong Zhang Jian, and Ming-Chih Chen, “Low-Cost FIR Filter Designs Based on Faithfully-Rounded Truncated Multiple Constant Multiplications-Accumulation,” IEEE Trans. Circuits and Systems, Part-II, vol. 60, no. 5, pp. 287-291, May 2013.
Chia-Sheng Wen, Yan-Haw Chen, Trieu-Kien Truong, and Shen-Fu Hsiao, “A Nearly Constant Delay and Low Power VLSI Design of a Pipeline Reed-Solomon Encoder for Storage and Communication Systems,” Journal of the Chinese Institute of Engineers, vol. 36, no. 6, pp. 771-786, Sept. 2013.
2015
Shen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, and Pramod Kumar Meher, “Table-Size Reduction Methods for Faithfully-Rounded Look-Up-Table-Based Multiplierless Function Evaluation,” IEEE Trans. Circuits and Systems, Part-II, vol. 62, no. 5, pp. 466-470, May 2015.
2016
Shen-Fu Hsiao, Chia-Sheng Wen, Yi-Hau Chen, and Kuei-Chun Huang, “Hierarchical Multipartite Function Evaluation”, accepted by IEEE Trans. Computers, May 2016.
2017
Shen-Fu Hsiao, Chia-Sheng Wen, Yi-Hau Chen, and Kuei-Chun Huang, “Hierarchical Multipartite Function Evaluation,” IEEE Trans. Computers, vol. 66, no. 1, pp. 89-99, Jan. 2017.
2020
Shen-Fu Hsiao, Kun-Chih Chen, Chih-Chien Lin, Hsuan-Jui Chang, and Bo-Ching Tsai, “Design of a Sparsity-Aware Reconfigurable Deep Learning Accelerator Supporting Various Types of Operations,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 10, no. 3, pp. 376-387, Sept. 2020.
研討會論文
1990
Jean-Marc Delosme and Shen-Fu Hsiao, “CORDIC Algorithms in Four Dimensions,” Advanced Signal Processing Algorithms, Architectures and Implementations, Proc. SPIE 1348, pp. 349-360, July 1990. (EI)
1991
Shen-Fu Hsiao and Jean-Marc Delosme, “The CORDIC Householder Algorithm,” Proc. 10-th IEEE Intl. Symposium on Computer Arithmetic, pp. 256-263, June 1991. (EI)
1993
Shen-Fu Hsiao and Jean-Marc Delosme, “Complex Singular Value Decomposition Using Multi-dimensional CORDIC Algorithms,” Proc. Intl. Conf. Parallel and Distributed Systems, pp. 487-493, Dec. 1993.
1994
Shen-Fu Hsiao and Jean-Marc Delosme, “Parallel Processing of Complex Data Using Quaternion and Pseudo-Quaternion CORDIC Algorithms,” Proc. IEEE Intl. Conf. Application Specific Array Processors, pp. 324-335, San Francisco, Aug. 1994. (EI)
Shen-Fu Hsiao, “VLSI Implementations of an Error-Correcting Encoder/Decoder,” Proc. 5-th VLSI/CAD Symposium, pp. 36-41, Aug. 1994.
Shen-Fu Hsiao and Vincent Tsai,“Parallel Eigenvalue Decomposition and Its VLSI Implementation,” Proc. 5-th VLSI/CAD Symposium, pp. 42-47, Aug. 1994.
Shen-Fu Hsiao, “Fixed-Point Analysis of the 4-D Householder CORDIC Algorithm,” Proc. Intl. Computer Symposium, pp. 612-617, Dec. 1994.
Shen-Fu Hsiao and Vincent Tsai, “VLSI Implementation of Fully Pipelined Hadamard Transform,” Proc. Intl. Computer Symposium, pp. 618-623, Dec. 1994.
1995
Shen-Fu Hsiao, “Adaptive Jacobi Method for Parallel Singular Value Decompositions,” Proc. IEEE Intl. Conf. Acoustics, Speech and Signal Processing, pp. 3203-3206, Detroit, May 1995. (EI)
Shen-Fu Hsiao, “A Radix-4 Pipelined FFT-Like Hadamard Transform Processor,” Proc. 6-th VLSI/CAD Symposium, pp. 233-236, Aug. 1995.
Shen-Fu Hsiao, and Vincent Tsai, “Design and Implementations of 4-D Unified CORDIC Processors,” Proc. 6-th VLSI/CAD Symposium, pp. 237-240, Aug. 1995.
Shen-Fu Hsiao and J.-C. Lin, “Redundant and On-Line CORDIC with Constant Scaling Factor and Its Implementations,” Proc. National Computer Symposium, pp. 106-113, Dec. 1995.
1996
C.N. Lee, T.-Y. Lee, S.-F. Hsiao and T.-C. Lu, “Performance Evaluation for Parallel Computing on Network Environments,” Proc. 1996 Workshop on Distributed System Technologies and Applications, pp. 237-246, May 1996.
Shen-Fu Hsiao and Peng-Chen Wang, “Power, Delay and Area Comparison of Adders and Multipliers at Both Circuit and Architecture Levels,” Proc. 7-th VLSI/CAD Symposium, pp. 245-248, Aug. 1996.
Shen-Fu Hsiao and Kuo-Chung Chen, “Efficient Eigenvalue Computation of Symmetric Tridiagonal Matrices on Heterogeneous Workstation Clusters,” Proc. of International Computer Symposium, Joint International Conf. on Distributed Systems, Software Engineering, and Database Systems, pp. 224-231, Dec. 1996.
1997
Shen-Fu Hsiao and Chung-Yi Yen, “New Unified VLSI Architectures for Computing DFT and Other Transforms,” Proc. ICASSP’97, IEEE International Conf. on Acoustics, Speech and Signal Processing, pp. 615-618, Munich, Germany, Apr. 1997. (EI)
Shen-Fu Hsiao and Ren-Je Shiu, “Efficient Implementation of Matrix Triangularization and Symmetric Matrix Tridiagonalization on Heterogeneous Workstation Clusters,” Proc. 1997 Workshop on Distributed System Technologies and Applications, pp. 357-366, May 1997.
Shen-Fu Hsiao and Jen-Yin Chen, “VLSI Implementation of Digit-On-Line CORDIC with Constant Scaling Factor,” Proc. ISCAS’97, IEEE International Symposium on Circuits and Systems, pp. 2068-2071, Hong Kong, June 1997. (EI)
Shen-Fu Hsiao and Chung-Yi Yen, “Power, Speed and Area Comparison of Several New DFT Architectures,” Proc. ISCAS’97, IEEE International Symposium on Circuits and Systems, pp. 2577-2580, Hong Kong, June 1997. (EI)
Shen-Fu Hsiao and Jen-Yin Chen, “VLSI Implementation of a High-Throughput CORDIC Processor for Both Angle Calculation and Vector Rotation,” Proc. IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), pp. 227-231, June 1997.
1998
Shen-Fu Hsiao, Chung-Yi Liu, and Jiang-Ming Tseng, “Analysis and Implementation of Data Partition and Load Balancing for Matrix Multiplication on Both Controllable and Non-controllable Network of Workstations,” Proc. 1998 Workshop on Distributed System Technologies and Applications, pp. 501-510, May 1998.
Wen-Chen Huang, Shen-Fu Hsiao, Chungnan Lee, and Cheng-Chung Hsu, “A Hybrid W-Transform-Based Coding and Its VLSI Realization for Image Compression,” Digest of Tech. Papers, IEEE Int’l Conf. Consumer Electronics, pp. 44-45, Los Angeles, June 1998. (EI)
Shen-Fu Hsiao and Jia-Siang Yeh, “Automatic Logic/Circuit Synthesizer Based on High-Performance and Flexible Pass-Transistor Cell Library,” Proc. 1998 International Conference on Chip Technology, pp. 79-86, Apr. 1998.
Shen-Fu Hsiao and Ming-Rong Jiang, “High-Performance Multiplier Synthesizer Based on Optimized Partial Product Reduction Tree,” Proc. 9th VLSI Design/CAD Symposium, pp. 23-26, Aug. 1998.
Shen-Fu Hsiao and Jia-Siang Yeh, “High Performance Multiplexer-Based Logic Synthesis Using Pass-Transistor Circuits,” Proc. 9th VLSI Design/CAD Symposium, pp. 19-22, Aug. 1998.
Shen-Fu Hsiao and Wie-Ren Shiue, “New Hardware-Efficient Architectures for Discrete Fourier Transform,” Proc. 9th VLSI Design/CAD Symposium, pp. 427-430, Aug. 1998.
Shen-Fu Hsiao, Chung-Yi Liu, and Jen-Yin Chen, “Design, Implementation and Error Analysis of Redundant CORDIC Processors for Fast Vector Rotation and Trigonometric Function Evaluation,” Proc. International Computer Symposium, Workshop on Computer Architecture, pp. 65-72, Dec. 1998. (Best Paper Award of Computer Society)
1999
Shen-Fu Hsiao and Wei-Ren Shiue, “New Hardware-Efficient Algorithms and Architectures for Computation of 2-D DCT on Linear Systolic Arrays,” Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP’99), Vol. 6, pp. 3517-3520, Phoenix, Mar. 1999. (EI)
Wei-Ren Shiue and Shen-Fu Hsiao, “A High-Throughput, Low-Power Architecture and its VLSI Implementation for DFT/IDFT Computation,” Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP’99), Vol. 4, pp. 1929-1932, Phoenix, Mar. 1999. (EI)
Shen-Fu Hsiao, “A High-Speed Constant-Factor Redundant CORDIC Processor without Extra Correcting or Scaling Iterations,” Proc. IEEE International Symposium on Circuits and Systems (ISCAS’99), Vol. 1, pp. 455-458, Orlando, May 1999. (EI)
Shen-Fu Hsiao and Ming-Rong Jiang, “An Efficient Synthesizer for Generation of Fast Parallel Multipliers,” Proc. of IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), pp. 66-69, June 1999.
Shen-Fu Hsiao,Wei-Ren Shiue, and Jian-Ming Tseng, “A Cost-Efficient and Fully-Pipelinable Linear Architecture for Discrete Cosine Transform,” Digest of Technical Papers of IEEE International Conference on Consumer Electronics (ICCE’99), pp. 60-61, Los Angeles, June 1999. (EI)
Tso-Bing Juang and Shen-Fu Hsiao, “A Low Power and Fast CORDIC Processor for Vector Rotation,” IEEE Proc. 42nd Midwest Symposium on Circuits and Systems (MWSCAS’99), pp. 81-83 Las Cruces, U.S.A., Aug. 1999.
C.-C. Wang, S.-H. Chen, S.-F. Hsiao, and C.-L. Wu, “Design and Performance Verification of ALUs for 64-bit 8-Isuue Superscaler Microprocessors Using 0.25um CMOS Technology,” Proc.1999 The 6th IEEE International Conference on Electronics, Circuits and Systems (ICECS’99), pp. 1217-1220, Sept. 1999.
Shen-Fu Hsiao and Chun-Yi Lau, “A High-Speed Universal Arithmetic Processor Based on Redundant CORDIC with Constant Scaling Factor and Merged Scaling Operation,” Proc. 10-th VLSI/CAD Symposium, pp. 61-65, Aug. 1999.
Shen-Fu Hsiao and Jian-Ming Tseng, “Direct Implementation of N x N 2-D DCT on a Pipelinable Linear-Array without Intermediate Transpose Memory,” Proc. 10-th VLSI/CAD Symposium, pp. 255-258, Aug. 1999.
Shen-Fu Hsiao and Jian-Ming Tseng, “Direct Implementation of 2-D DCT on a Low-Cost Linear-Array Architecture without Intermediate Transpose Memory,” Proc. IEEE Workshop on Signal Processing Systems (SiPS’99), pp. 90-99, Oct. 1999. (EI)
C.-C. Wang, Y.-L. Tseng, Y.-H. Hsueh, S.-K. Huang, and S.-F. Hsiao, “Universal Current Integration Module IC Design for Smart Battery Management of Mobile Handsets,” Proc. National Computer Symposium (NCS’99), Vol. I, pp. A-525-531, Dec. 1999.
2000
Shen-Fu Hsiao, Jia-Siang Yeh and Da-Yen Chen, “High-Performance Multiplexer-Based Logic Synthesis Using Pass-Transistor Logic”, Proc. IEEE Int’l Symp. on Circuits and Systems (ISCAS’2000), Vol. II, pp. 325-328, Geneva, Switzerland, May 2000. (EI)
Tso-Bing Juang and Shen-Fu Hsiao, “Discussions on the CORDIC Processor Using Leading Zero Detectors,” IEEE Proc. Southwest Symposium on Mixed-Signal Design (SSMSD'2000), pp. 175-178, San Diego, U.S.A., Feb., 2000.
Shen-Fu Hsiao and Wei-Ren Shiue, “Low-Cost Unified Architectures for the Computation of Discrete Trigonometric Transforms,” Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing(ICASSP’2000), Vol. IV, pp. 3299-3302, Istanbul, Greeece, June 2000. (EI)
Shen-Fu Hsiao, Yor-Chin Tai, and Kai-Hsiang Chang, “VLSI Design of an Efficient Embedded Zerotree Wavelet Coder with Function of Digital Watermarking,” Digest of Technical Papers of IEEE International Conference on Consumer Electronics (ICCE), pp. 186-187, June 2000. (EI)
Chao-Chuan Huang, Tso-Bing Juan and Shen-Fu Hsiao, “CORDIC-Based Signed-Bit Predictable SIN/COS Generator,” Proc. 11th VLSI Deisgn/CAD Symp., pp. 299-303, Aug. 2000.
Mu-San Chung, Kai-Hsiang Chang and Shen-Fu Hsiao, “Robust Spatial-Domain Watermarking Methods Based on a Weighting Table with Fine Tune Technique,” Proc. International Computers Symposium (ICS’2000), Dec. 2000.
2001
Shen-Fu Hsiao, Tso-Bing Juang, Jeng Hsium Jan, and Ming Yu Tsai, “A Multiplier-Based Arithmetic Function Generator for Digital Signal Processing Applications,” Proc. 12thVLSI/CAD Symp., Paper No. B2-7, Aug. 2001.
Ming-Yu Tsai, Tso Bing Juang and Shen-Fu Hsiao, “Novel High-Performance and Area-Efficient D-Flip-Flop Circuits,” Proc. 12th VLSI/CAD Symp., Paper No. C3-12, Aug. 2001.
Tso-Bing Juan, Ming-Ju Tsia and Shen-Fu Hsiao, “Area-Efficient Carry-Save Full Adder Design Using Pass Transistors,” Proc. International Symposium on Integrated Circuits, Systems and Devices, pp. 173-176, Singapore, Sept. 2001.
Tso-Bing Juan, Chau-Chuang Huang, and Shen-Fu Hsiao, “Design of a CORDIC-Based Sin/Cos Intellectual Property Using Predictable Sign Bits,” Proc. 27-th European Solid-State Circuits Conf (ESSCIRC) , pp. 292-295, Villach, Austria, Sept. 2001.
2002
Ming-Yu Tsai, Chia-Sheng Wen, and Shen-Fu Hsiao, “High-Performance Logic Synthesis Based on Pass-Transistor Logic,” Proc. 13th VLSI/CAD Symp., Aug. 2002.
Ming-Chih Chen, Shen-Fu Hsiao, and Cheng-Hsien Yang, “Design and Implementation of a Video-Oriented Network-Interface-Card System,” Proc. 13th VLSI/CAD Symp., Aug. 2002.
Tso-Bing Juang, Jeng-Hsin Jan, Ming-Yu Tsai, and Shen-Fu Hsiao, “A High-Performance Function Generator for Multiplier-Based Arithmetic Operations,” Proc. IEEE 3rd Asia-Pacific Conf. on Advanced System Integrated Circuits (AP-ASIC), pp. 331-334, Aug. 2002.
Ming-Chih Chen, Shen-Fu Hsiao, and Cheng-Hsien Yang, “Design and Implementation of a Specific Network-Interface-Card for Accelerating Video Delivery,” Proc. International ASIC/SOC Conference, Sept. 2002.
Ming-Chih Chen, Shen-Fu Hsiao, and Cheng-Hsien Yang, “Design and Implementation of a High-Performance Video-Oriented Network-Interface-Card System,” Workshop on Application Specific Processors (WASP), Micro-35 Workshop, Istanbul, Turkey, Nov. 2002.
Tso-Bing Juang, Jeng-Hsin Jan, Ming-Yu Tsai, and Shen-Fu Hsiao, “Partitioning Methodology of the Final Adder in a Tree Structure Parallel Multiplier Generator,” Proc. IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), pp. 471-474, Singapore, Dec. 2002.
2003
Ming-Chih Chen, Shen-Fu Hsiao, and Cheng-Hsien Yang, Jan. 2003,“Design and Implementation of A Video-Oriented Network-Interface-Card System,” Proc. of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Japan, Jan. 2003.
Shen-Fu Hsiao and Tso-Bing Juang,“A ROM-Free CORDIC-Based Sine/Cosine Function Generator Based on Concurrently Predicted Rotation Directions,” Proc. 14th VLSI/CAD Symp., pp. 237-240, Aug. 2003.
Ming-Chih Chen, Shen Fu Hsiao, and Ming-Yu Tsai, “Architectural Optimization for the forward and Inverse MixColumn Operations in Rijndael AES,” Proc. 14th VLSI/CAD Symp., Aug. 2003.
Shen-Fu Hsiao and Yu-Hen Hu, “High-Radix Low-Complexity Architectures for Long-Length DCT Using Conventional Arithmetic and ROM-Based Distributed Arithmetic,” Proc. IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), pp. 168-171, Oct. 2003.
Ming-Chih Chen and Shen Fu Hsiao, “Efficient Substructure Sharing Method for the Forward and Inverse MixColumns Operations in Rijndael AES”, Proc. International Conference on Informatics, Cybernetics, and Systems (ICICS-2003), Dec. 2003.
Tso-Bing Juang, Shen-Fu Hisao and Ming-Yu Tsai, “Design of Fixed-Length Multipliers Using Radix-2 Signed-Digit Redundant Numbers,” Proc. International Conference on Informatics, Cybernetics, and Systems (ICICS), pp. 1238-1242, Dec. 2003.
2004
Shen-Fu Hsiao and Ming-Chih Chen, “Two Efficient Area Reduction Methods for Implementations of the Rijndael Advanced Encryption Standard,” Proc. IEEE Asia-Pacific Conf. on Circuits and Systems (APCCAS), Vol 1, pp. 353-356, Dec. 2004.
Tso-Bing Juang, Shen-Fu Hsiao, Shiann-Rong Kuang, and Ming-Yu Tsai, “Low-error Carry-Free Fixed-Width Multipliers and Their Application to DCT/IDCT,” Proc. IEEE Asia-Pacific Conf. Circuits and Systems (APCCAS), Vol. 1, pp. 457-460, Dec. 2004.
2005
Shen-Fu Hsiao, Ming-Yu Tsai, Ming-Chih Chen, and Chia-Sheng Wen, “An Efficient Pass-Transistor-Logic Synthesizer Using Multiplexers and Inverters Only,” Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Vol. 3, pp.2433-2436, Kobe, Japan, May 2005.
2006
Shen-Fu Hsiao, Yo-Chi Chen, Ming-Yu Tsai, and Tze-Chong Cheng, “Novel Memory Organization and Circuit Designs for Efficient Data Access in Applications of 3D Graphics and Multimedia Coding,” Proc. IEEE Intl. Workshop on Memory Technology, Design and Testing (MTDT’2006), pp. 34-39, Aug., 2006.
Shen-Fu Hsiao, Ting-Yuan Huang, and Tze-Chieng Tieng, “Design and Verification of a Platform-Based Low-Cost 3D Graphics Geometry Engine Using Area-Reduced Arithmetic Units,” Proc. 17-th VLSI Design/CAD Symposium, A1-12, Aug. 2006.
Shen-Fu Hsiao, Sze-Yun Lin, Tze-Chorng Cheng, and Ming-Yu Tsai, “An Automatic Cache Generator Based on Content-Addressable Memory,” Proc. IEEE Asia-Pacific Conf. on Circuits and Systems (APCCAS’2006), pp.1313-1316, Dec. 2006.
Shen-Fu Hsiao, Ming-Yu Tsai, and Chia-Sheng Wen, “Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits,” Proc. IEEE Asia-Pacific Conf. on Circuits and Systems (APCCAS’2006), pp. 1631-1634, Dec. 2006.
Jin-Lin Liu, Shiann-Rong Kuang, and Shen-Fu Hsiao, “Integrated System Architecture Synthesis of Distributed Embedded Systems for Multimedia Applications,” Proc. International Workshop on Computer Architecture, VLSI, and Embedded Systems, Dec. 2006.
2007
Ming-Yu Tsai, Chia-Sheng Wen, and Shen-Fu Hsiao, “Multple-Input XOR/XNOR Circuit Design Using Pass-Transistor Logic and Its Application in Cryptography,” Proc. 18-th VLSI Design/CAD Symposium, Aug. 2007.
Ping-Chung Wei, Ching-Pin Lin, and Shen-Fu Hsiao, “Performance Comparisons and Tradeoffs of Table-Based Arithmetic Function Evaluators,” Proc. 18-th VLSI Design/CAD Symposium, Aug. 2007.
Ruei-Ting Gu, Tse-Chen Yeh, Wei-Sheng Hunag, Ting-Yun Huang, Chung-Hua Tsai, Chung-Nan Lee, Ming-Chao Chiang, Shen-Fu Hsiao, Yun-Nan Chang, Ing-Jer Huang, “A Low Cost Tile-based 3D Graphics Full Pipeline with Rreal-time Performance Monitoring Support for OpenGL ES in Consumer Electronics,” Proc. IEEE Intl. Symp. Consumer Electronics (ISCE), pp. 1-6, June 2007.
2008
Shen-Fu Hsiao, Ming-Yu Tsai, and Chia-Sheng Wen, “Transistor Sizing and Layout Merging of Basic Cells in Pass Transistor Logic Cell Library,” Proc. IEEE Intl. Symp. on VLSI Design, Automation and Testing (VLSI-DAT), pp. 89-92, Apr. 2008. (EI)
Shen-Fu Hsiao, Ming-Yu Tsai, and Chia-Sheng Wen, “Area-Oriented Pass-Transistor Logic Synthesis Using Buffer Elimination and Layout Compaction,” Proc. IEEE Intl. Symp. on Circuits and Systems (ISCAS), Seattle, pp. 2022-2025, Seattle, USA, May 2008. (EI)
Shen-Fu Hsiao, Ping-Chung Wei, and Ching-Pin Lin, “An Automatic Hardware Generator for Special Arithmetic Functions Using Various ROM-Based Approximation Approaches,” Proc. IEEE Intl. Symp. on Circuits and Systems (ISCAS), pp. 468-471, Seattle, USA, May 2008. (EI)
Ming-Chih Chen, and Shen-Fu Hsiao, “Efficient Hardware Realization of Transformations in Advanced Encryption Standard Using a New Common-Subexpression-Elimination Algorithm,” Proc. of The 16th National Conference on Automation Technology, pp. 1201-1205, June 2008.
Shen-Fu Hsiao, Yuan-Nan Chang, Tze-Ching Tien, and Kun-Chih Chen, “Efficient Pre-Clipping and Clipping Algorithms for 3D Graphics Geometry Computation,” Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 522-525, Macau, Nov. 2008.
Shen-Fu Hsiao, Hsin-Mau Lee, Yen-Chun Cheng, and Ming-Yu Tsai, “Efficient Designs of Floating-Point CORDIC Rotation and Vectoring Operations,” Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 1422-1425, Macau, Nov. 2008.
Liang-Bi Chen, Tsung-Yu Ho, Ing-Jer Huang, Yun-Nan Chang, Steve W. Haga, Jin-Hua Hong, Shen-Fu Hsaio, Shiann-Rong Kuang, Ko-Chi Kuo, and Chung-Nan Lee, “The Development of an Energy-awared Mobile 3D Graphics SoC with Real-time Performance/Energy Monitoring and Control,” Proc. Intl. SOC Design Conference (ISOCC), vol. I, pp. 234-237, Nov. 2008.
2009
Ming-Chih Chen and Shen-Fu Hsiao, “Low Cost Design of an Advanced Encryption Standard (AES) Processor Using a New Common-Subexpression-Elimination Algorithm,” Proc. 14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2009), pp. 242-247, Okinawa, Japan, Mar. 2009.
Kun-Chih Chen and Shen-Fu Hsiao, “Low-Cost Design of Non-Uniform Symmetric Bipartite Table Method Using Hierarchical Segmentation,” Proc. 20th VLSI Design/CAD Symp., Paper No. 9-6, Aug. 2009.
Shen-Fu Hsiao and Keng-Hsien Lin, “Design of an Efficient Clipping Engine for OpenGL-ES 2.0 Vertex Shaders in 3D Graphics Systems,” Proc. 20th VLSI Design/CAD Symp., Paper No. P1-2, Aug. 2009.
2010
Hou-Jen Ko, Shen-Fu Hsiao, and Wen-Liang Huang, “A New Non-Uniform Segmentation and Addressing Remapping Strategy for Hardware-Oriented Function Evaluators Based on Polynomial Approximation,” Proc. Intl. Symp. Circuits and Systems (ISCAS), pp. 4153-4156, Paris, France, May 2010.
Shen-Fu Hsiao, Chia-Sheng Wen and Ming-Yu Tsai, “Low-Cost Design of Reciprocal Function Units Using a Hybrid Polynomial Interpolation and Newton-Raphson Approach,” Proc. 20th VLSI Design/CAD Symp., Paper No. P2-7, Aug. 2010.
Pramod Kumar Meher, Shen-Fu Hsiao, Chia-Sheng Wen, and Ming-Yu Tsai, “Low-Cost Design of Serial-Parallel Multipliers Over GF(2m) Using Hybrid Pass-Transistor Logic (PTL) and CMOS Logic,” Proc. IEEE Intl. Symp. on Electronic System Design (ISED), pp. 131-134, Dec. 2010.
Shen-Fu Hsiao, Chia-Sheng Wen, and Hsin-Mau Lee, “Implementation of Floating-Point CORDIC Rotation and Vectoring Based on Look Up Tables and Multipliers,” Proc. Intl. Symp. On Next-Generation Electronics (ISNE), pp. 44-47, Nov. 2010.
Shen-Fu Hsiao, Chia-Sheng Wen and Ming-Yu Tsai, “Low-Cost Design of Reciprocal Function Units Using Shared Multipliers and Adders for Polynomial Approximation and Newton Raphson Interpolation,” Proc. Intl. Symp. On Next-Generation Electronics (ISNE), pp. 40-43, Nov. 2010.
Shen-Fu Hsiao, Chia-Sheng Wen, Ming-Yu Tsai, and Ming-Chih Chen, “Automatic Generation of High-Performance Multiple-Input XOR/XNOR Circuits and Its Application in Advanced Encryption Standard,” Proc. Intl. Symp. On Next-Generation Electronics (ISNE), pp. 77-80, Nov. 2010.
Shen-Fu Hsiao, Chia-Sheng Wen, and Kun-Chih Chen, “Design of Table-Based Function Evaluators with Reduced Memory Size Using a Bottom-Up Non-Uniform Segmentation Method,” Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 1079-1082, Dec. 2010.
2011
Shen-Fu Hsiao, Chan-Feng Chiu, and Chia-Sheng Wen, “Design of a Low-Cost Floating-Point Programmable Vertex Processor for Mobile Graphics Applications Based on Hybrid Number System,” Proc. Int’l Conf. Integrated Circuit Design & Technology (ICICDT), pp. 1-4, May 2011.
Shen-Fu Hsiao, Chia-Sheng Wen, Cheng-Han Lee, Yen-Chun Cheng, Wei-Cheng Syu, “Architectural Design Trade-Offs for Vector Rotation in Different Precision Requirements,” Proc. 21th VLSI Design/CAD Symp., Aug. 2011.
Shen-Fu Hsiao, Cheng-Han Lee, Yen-Chun Cheng, Andrew Lee, “Designs of Angle-Rotation in Digital Frequency Synthesizer/Mixer Using Multi-Stage Architectures,” Proc. IEEE 45th Asilomar Conference on Signals, Systems and Computers, pp. 2181-2185, Pacific Grove, USA., Nov. 2011.
2012
Shen-Fu Hsiao, Jin-Wen Cheng, Wen-Ling Wang, and Guan-Fu Yeh, “Low Latency Design of Depth-Image-Based Rendering Using Hybrid Warping and Hole-Filling,” Proc. IEEE Intl. Symp. Circuits and Systems (ISCAS), pp. 608-611, Korea, May 2012.
Shen-Fu Hsiao, Hou-Jen Ko, Yu-Ling Tseng, and Chia-Sheng Wen, “Hardware-Efficient Function Evaluation Based on Joint Consideration of All Error Source,” Proc. 22th VLSI Design/CAD Symp., Aug. 2012..
Shen-Fu Hsiao and Guan-Fu Yeh, “Software and Hardware Designs of a Vehicle Detection System with Machine Learning,” Proc. 25th IPPR Conf. on Computer Vision, Graphics, and Image Processing, Aug. 2012. (Best paper award)
Shen-Fu Hsiao, Chia-Sheng Wen, Cheng-Han Lee, and Andrew Lee, “Low-Cost Designs of Rectangular to Polar Coordinate Converters for Digital Communication,” Proc. of IEEE Asia-Pacific Conf. Circuits and Systems (APCCAS), pp. 408-411, Kaohsiung, Taiwan, Dec. 2012.
Shen-Fu Hsiao, Chi-Guang Lin, Po-Han Wu, and Chia-Sheng Wen, “Asynchronous AHB Bus Interfaces Designs in a Multiple-Clock-Domain Graphics System,” Proc. of IEEE Asia-Pacific Conf. Circuits and Systems (APCCAS), pp. 511-514, Kaohsiung, Taiwan, Dec. 2012.
2013
Shen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, and Li-Yao Chen, “Design of a Programmable Vertex Processor in OpenGL ES 2.0 Mobile Graphics Processing Units,” Proc. IEEE Intl. Symp. on VLSI Design, Automation and Testing (VLSI-DAT), Hsinchu, Taiwan, pp. 1-4, Apr. 2013.
Shen-Fu Hsiao, Hou-Jen Ko, Yu-Ling Tseng, and Chia-Sheng Wen, “A New Design Methodology for Rounding and Hardware Minimization in Look-Up-Table-Based Arithmetic Function Evaluation,” Proc. 18th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 149-152, Sapporo, Japan, Oct. 2013.
2014
Shen-Fu Hsiao, Wen-Ling Wang, and Po-Sheng Wu, “VLSI Implementation of Stereo Matching Based on Dynamic Programming,” Proc. IEEE Intl. Symp. on VLSI Design, Automation and Testing (VLSI-DAT), pp. 142-145, Hsinchu, Taiwan, Apr. 2014.
Shen-Fu Hsiao and Pu-Cheng Wu, “Design of Low-Leakage Multi-Port SRAM for Register File in Graphics Processing Unit,” Proc. IEEE Intl. Symp. Circuits and Systems (ISCAS), pp. 2181-2184, Melbourne, Australia, June 2014.
Shen-Fu Hsiao, Guan-Fu Yeh, and Je-Chi Chen, “Design and Implementation of Multiple-Vehicle Detection and Tracking Systems with Machine Learning,” Proc. 17th Euromicro Conf. on Digital Systems Design (DSD), pp. 551-558, Verona, Italy, Aug. 2014.
Shen-Fu Hsiao, Chia-Sheng Wen, and Po-Han Wu, “Compression of Lookup Table for Piecewise Polynomial Function Evaluation,” Proc. 17th Euromicro Conf. on Digital Systems Design (DSD), pp, 279-284,Verona, Italy, Aug. 2014.
Shen-Fu Hsiao, Jun-Ming Huang, and Po-Sheng Wu, “VLSI Implementation of Belief-Propagation-Based Stereo Matching with Linear-Model Message Update,” Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 73-76, Ishigaki, Japan, Nov. 2014.
2015
Hsu-Kung Dow, Ching-Hua Huang, Chun-Hung Lai, Kai-Hsing Tsao, Sheng-Chih Tseng, Kun-Yi Wu, Ting-Hsuan, Ho-Chun Yang, Da-Jing Zhang Jain, Yun-Nan Chang, Steve Haga, Shen-Fu Hsiao, Ing-Jer Huang, Shiann-Rong Kuang, and Chung-Nan Lee, “An OpenGL ES 2.0 3D Graphics SoC with Versatile HW/SW Development Support,” Proc. Intl. Symp. VLSI Design, Automation and Test (VLSI-DAT), Apr. 2015.
Shen-Fu Hsiao, Po-Sheng Wu, and Jun-Mao Chan, “VLSI Implementation of Feature Extraction in Image Processing and Computer Vision,” Proc. Intl. Conf. Applied System Innovation, Osaka, Japan, May 2015.
Shen-Fu Hsiao, Kai-Hsiang Tsao, and Shang-Yu Li, “Low-Power and High-Performance Design of OpenGL ES 2.0 Graphics Processing Unit for Mobile Applications,” Proc. IEEE Intl. Conf. on Digital Signal Processing (DSP), Singapore, July 2015.
Shen-Fu Hsiao, Jun-Mao Chan, and Ching-Hui Wang, “VLSI Implementation of HOG for Pedestrian Detection,” Proc. 26th VLSI Design/CAD Symp., Aug. 2015.
2016
Shen-Fu Hsiao and Kuei-Chun Huang, “Dual-Precision Function Evaluation Based on Piecewise Polynomial Approximation,” Proc. 27th VLSI Design/CAD Symp., Aug. 2016.
Shen-Fu Hsiao and Kuei-Chun Huang, “Low-Power Dual-Precision Table-Based Function Evaluation Supporting Dynamic Precision Changes,” to appear in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Oct. 2016.
Shen-Fu Hsiao, Jun-Mao Chan, and Ching-Hui Wang, “Hardware Design of Histograms of Oriented Gradients Based on Local Binary Pattern and Binarization,” to appear in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Oct. 2016.
2017
Shen-Fu Hsiao and Yi-Hau Chen, “Memory Optimization for Table-Bound Function Evaluation Using Multi-Level Table Decomposition,” Proc. VLSI/CAD Symp., Aug., 2017.
Shen-Fu Hsiao and Yi-Hau Chen, “Memory Optimization for Table-Bound Function Evaluation Using Multi-Level Table Decomposition,” Proc. VLSI/CAD Symp., Aug., 2017.
2018
Shen-Fu Hsiao and Chih-Hsuan Chang, “Hardware Design of Disparity Computation for Stereo Vision Using Guided Image Filtering,” Proc. Intl. Symp. VLSI Design, Automation and Test (VLSI-DAT), Apr. 2018.
Shen-Fu Hsiao, Yi-Hau Chen, and Kun-Chih Chen, “Optimization of Lookup Table Size in Table-Bound Design of Function Computation,” Proc. IEEE Intl. Symp. Circuits and Systems (ISCAS), Florence, Italy, May, 2018.
Shen-Fu Hsiao, Yi-Hau Chen, and Kun-Chih Chen, “Optimization of Lookup Table Size in Table-Bound Design of Function Computation,” Proc. IEEE Intl. Symp. Circuits and Systems (ISCAS), Florence, Italy, May, 2018.
Shen-Fu Hsiao and Chen-Yen Tsai, “Design and Implementation of Low-Cost LK Optical Flow Computation for Images of Single and Multiple Levels,” Euromicro Conf. on Digital System Design (DSD), Prague, Czech Republic, Aug. 2018.
Shen-Fu Hsiao, Chen-Yen Tsai, and Pei-Hsuen Wu, “Design of Real-Time Hierarchical Optical Flow Estimation with Image Pyramid,” VLSI/CAD Symp., Aug. 2018.
Shen-Fu Hsiao and Pei-Hsuen Wu, “Analysis of Memory Access Energy for Designing Power-Efficient Deep Neural Network Hardware Accelerators,” VLSI/CAD Symp., Aug. 2018.
Shen-Fu Hsiao and Pei-Hsuen Wu, “Design Trade-Off of Internal Memory Size and Power in Deep Neural Network Hardware Accelerators,” IEEE Global Conf. on Consumer Electronics, Nara, Japan, Oct. 2018.
2019
Shen-Fu Hsiao and Pei-Hsuen Wu, “Design Trade-Off of Internal Memory Size and Power in Deep Neural Network Hardware Accelerators,” IEEE Global Conf. on Consumer Electronics, Nara, Japan, Oct. 2018.
Shen-Fu Hsiao, Kuei-Chin Huang, and Yu-Hong Chen, “Multi-Precision Table-Addition Designs for Computing Nonlinear Functions in Deep Neural Networks,” IEEE Asia Pacific Conf. on Circuits and Systems (APCCAS), Bangkok, Thailand, Nov. 2019.
Shen-Fu Hsiao, Kuei-Chin Huang, and Yu-Hong Chen, “Multi-Precision Table-Addition Designs for Computing Nonlinear Functions in Deep Neural Networks,” IEEE Asia Pacific Conf. on Circuits and Systems (APCCAS), Bangkok, Thailand, Nov. 2019.
2020
Shen-Fu Hsiao, Kuei-Chin Huang, and Yu-Hong Chen, “Multi-Precision Table-Addition Designs for Computing Nonlinear Functions in Deep Neural Networks,” IEEE Asia Pacific Conf. on Circuits and Systems (APCCAS), Bangkok, Thailand, Nov. 2019.
Shen-Fu Hsiao and Hsuan-Jui Chang, “Sparsity-Aware Deep Learning Accelerator Design Supporting CNN and LSTM Operations,” IEEE Intl. Symp. Circuits and Systems (ISCAS), Oct. 2020.
Shen-Fu Hsiao, Chia-Yang Wong, and Yu-Chang Chen, “Hardware Efficient Function Computation Based on Optimized Piecewise Polynomial Approximation,” IEEE Intl. Symp. Circuits and Systems (ISCAS), Oct. 2020.
2021
Shen-Fu Hsiao, Yu-Chang Chen, and Yu-Che Yen, “Efficient Quantization and Multi-Precision Design of Arithmetic Components for Deep Learning”, IEEE Intl. Symp. Circuits and Systems (ISCAS), May 2021.
Shen-Fu Hsiao, Jian-Ming Chen, Yu-Hong Chen, Hung-Ching Li, and Yi Hsu, “Comparison of Digit-Serial and Bit-Level Designs for Acceleration of Convolutional Neural Network Computation”, IEEE Intl. Symp. Circuits and Systems (ISCAS), May 2021.
Shen-Fu Hsiao and Yu-Che Yen, “Quantization of Deep Neural Network Models Considering Per-Layer Computation Complexity for Efficient Execution in Multi-Precision Accelerators,” IEEE Intl. Conf. Consumer Electronics-Taiwan (ICCE-TW), June 2021.
Shen-Fu Hsiao, Jyun-Liang Chen, Yi Hsu, and Xiang-Ting Huang, “Multi-threaded System Design of A Multi-Precision Deep Learning Accelerator on FPGA with Optimized Memory Usage,” IEEE Intl. Conf. Consumer Electronics-Taiwan (ICCE-TW), June 2021.
Shen-Fu Hsiao and Bo-Ching Tsai, “Efficient Computation of Depthwise Separable Convolution in MoblieNet Deep Neural Network Models,” IEEE Intl. Conf. Consumer Electronics-Taiwan (ICCE-TW), June 2021.
專書、技術報告
1998
A contributor in the book “High Performance VLSI Signal Processing - Innovative Architectures and Algorithms,” ed. K. J. Ray Liu and K. Yao, IEEE Press, 1998.
2017
A contributor in the book “Arithmetic Circuits for DSP Applications,” by P. K. Meher and T. Stouraitis, IEEE Press, 2017.