The performance of Si LSIs has been enhanced over 40 years by increasing the number of transistors, according to the Moore's law. However, the device scaling is approaching to the physical limitation because the gate length has been already scaled to less than 20 nm. In the next 10 - 20 years, the device scaling might end, leading to no further enhancement in the LSI performance by the device scaling.

On the other hand, much more computing power will be strongly required because of the emergence of new IoT and AI applications. Hence, the next-generation computing technologies have intensively been investigated to enhance the LSI performance without the device scaling. We are conducting such researches on next-generation semiconductor devices for AI and IoT applications. We are mainly focusing on the the technology development based on Si CMOS, and the heterogeneous integration of III-V semiconductors, Ge, and ferroelectric materials on the Si platform. 

Main research

• HfO2-based Ferroelectric devices

• Reservoir computing based on ferroelectric devices

• Ultra-thin III-V MOSFET for CMOS 3D-integration

• Ultra-thin Ge MOSFET for CMOS 3D-integration

• Understanding of Si CMOS operation under ultra-low temperature for quantum computing application