Embedded Files
MPW Chip
MPW Chip
A Quarter-rate Single Loop CDR (Samsung 28㎚)
A Quarter-rate Single Loop CDR (Samsung 28㎚)
Designed by Jin-Ho Kim
A Low-Power Counter-based Digital CDR (Samsung 28㎚)
A Low-Power Counter-based Digital CDR (Samsung 28㎚)
Designed by Hyun-In Kim
A Single Loop Continuous-rate CDR with Unrestricted Frequency Acquistion (Samsung 28㎚)
A Single Loop Continuous-rate CDR with Unrestricted Frequency Acquistion (Samsung 28㎚)
Designed by Hyung-Wook Lee
Design of PAM4 Transmitter with Maximum Transition Elimination and Transition Compensation Technique (Samsung 28㎚)
Design of PAM4 Transmitter with Maximum Transition Elimination and Transition Compensation Technique (Samsung 28㎚)
Designed by Kyung-Min Ko
Design of 20Gb/s NRZ/PAM4 Dual-Mode Receiver with Adaptive Non-speculative DFE having Extended Time Constraint (Samsung 28㎚)
Design of 20Gb/s NRZ/PAM4 Dual-Mode Receiver with Adaptive Non-speculative DFE having Extended Time Constraint (Samsung 28㎚)
Designed by Do-Hyun Kwon
10Gbps PAM4 Receiver with Successive Approximation Adaptive Threshold Voltage and Equalization Control Block (Samsung 65㎚)
10Gbps PAM4 Receiver with Successive Approximation Adaptive Threshold Voltage and Equalization Control Block (Samsung 65㎚)
Designed by Bong-Kyu Kim
Spread Spectrum Clock Generator with Dual tone Modulation Profile based on Hershey-Kiss Modulation Profile (Samsung 65㎚)
Spread Spectrum Clock Generator with Dual tone Modulation Profile based on Hershey-Kiss Modulation Profile (Samsung 65㎚)
Designed by Sung-Ho Kim
Design of 8bit, 5ps Two-Step Time to Digital Converter Using Pulse-Shifting Time Difference Repetition circuit (Magna 180㎚)
Design of 8bit, 5ps Two-Step Time to Digital Converter Using Pulse-Shifting Time Difference Repetition circuit (Magna 180㎚)
Designed by Chan-Han Rho
PAM4 Transmitter with Transition Detecting Compensation and Receiver with CTLE and 1-tap DFE (Samsung 65㎚)
PAM4 Transmitter with Transition Detecting Compensation and Receiver with CTLE and 1-tap DFE (Samsung 65㎚)
Designed by Min-Ji Kim
A Reference-less Clock and Data Recovery Circuit with Bidirectional Frequency Detector (Magna 180㎚)
A Reference-less Clock and Data Recovery Circuit with Bidirectional Frequency Detector (Magna 180㎚)
Designed by Ho-jun Lee
A Counting-based Reference Clock less Clock/Data Recovery Circuit Design for High-Speed Serial Links (Magna 180㎚)
A Counting-based Reference Clock less Clock/Data Recovery Circuit Design for High-Speed Serial Links (Magna 180㎚)
Designed by Kyung-Sub Son
On-Chip Jitter Tolerance Measurement Technique for CDR (Samsung 65㎚ CMOS)
On-Chip Jitter Tolerance Measurement Technique for CDR (Samsung 65㎚ CMOS)
Designed by Kyung-Sub Son
Wireless Power & Data Transfer circuit for Bio Device (Dongbu 0.35㎛)
Wireless Power & Data Transfer circuit for Bio Device (Dongbu 0.35㎛)
Designed by Tae-Gwon Yoon
Reference-less Clock and Data Recovery using a PWM Signaling with Improved Bit Error Rate (SAMSUNG 65㎚ CMOS)
Reference-less Clock and Data Recovery using a PWM Signaling with Improved Bit Error Rate (SAMSUNG 65㎚ CMOS)
Designed by Eun-Ho Yang
A Spread Spectrum Clock Generator using Hershey-Kiss Profile (Dongbu 110㎚)
A Spread Spectrum Clock Generator using Hershey-Kiss Profile (Dongbu 110㎚)
Designed by Seung-Wook Oh
1.62/2.7/5.4Gbps Clock and Data Recovery (SMIC 65㎚)
1.62/2.7/5.4Gbps Clock and Data Recovery (SMIC 65㎚)
Designed by Jin-Cheol Seo
Spread Spectrum Clock Generator (SAMSUNG 0.13㎛)
Spread Spectrum Clock Generator (SAMSUNG 0.13㎛)
Designed by Hyung-Min Park
Phase modulation I/O (SAMSUNG 0.13㎛)
Phase modulation I/O (SAMSUNG 0.13㎛)
Designed by Hyung-Min Park
5.4/3.24Gbps Dual-rate CDR (0.18㎛ CMOS)
5.4/3.24Gbps Dual-rate CDR (0.18㎛ CMOS)
Designed by Jae-Wook Yoo
Audio Clock Regenerator (TSMC 0.18㎛)
Audio Clock Regenerator (TSMC 0.18㎛)
Designed by Sang-Ho Kim
A 1.7Gbps DLL-based Clock Data Recovery (0.35㎛ CMOS)
A 1.7Gbps DLL-based Clock Data Recovery (0.35㎛ CMOS)
Designed by Sang-Ho Kim
A 5-Gb/s Continuous-time Adaptive Equalizer and CDR (SAMSUNG 0.18㎛ CMOS)
A 5-Gb/s Continuous-time Adaptive Equalizer and CDR (SAMSUNG 0.18㎛ CMOS)
Designed by Tae-Ho Kim
A 2.7Gbps & 1.62Gbps Dual-Mode Clock and Data Recovery (0.18㎛ CMOS)
A 2.7Gbps & 1.62Gbps Dual-Mode Clock and Data Recovery (0.18㎛ CMOS)
Designed by Seung-won Lee
3Gbps SERDES
3Gbps SERDES
Designed by Yong-Woo Kim, Seung-won Lee
40Gbps CDR (TSMC RF 0.18㎛)
40Gbps CDR (TSMC RF 0.18㎛)
Designed by Gi-Hyeok Ha
SSCG Using modulation on VCO current source (Hynix 0.18㎛ CMOS)
SSCG Using modulation on VCO current source (Hynix 0.18㎛ CMOS)
Designed by Wan-Sik Lim
A Multi-Spread Ratio Spread Spectrum Clock Generator (TSMC 0.18㎛ CMOS)
A Multi-Spread Ratio Spread Spectrum Clock Generator (TSMC 0.18㎛ CMOS)
Designed by Il-Do Kim
3.125Gbps Reference-less Clock / Data Recovery using 4X Oversampling (TSMC 0.18㎛ CMOS)
3.125Gbps Reference-less Clock / Data Recovery using 4X Oversampling (TSMC 0.18㎛ CMOS)
Designed by Sung-Sop Lee
1.25Gbps Clock / Data Recovery with a Wide Frequency Tracking (0.25㎛ CMOS)
1.25Gbps Clock / Data Recovery with a Wide Frequency Tracking (0.25㎛ CMOS)
Designed by Jung-Young Lee
Multiphase PLL using a Vernier (0.18㎛ CMOS)
Multiphase PLL using a Vernier (0.18㎛ CMOS)
Designed by Jae-Gyu Sung
10GHz LC Tank Multiphase PLL (0.18㎛ CMOS)
10GHz LC Tank Multiphase PLL (0.18㎛ CMOS)
Designed by Jung-Young Lee
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