🔸 Objective:

      To verify the functional correctness of both accurate and approximate DSP modules using RTL simulation and measure the accuracy trade-offs.

🔸 Key Activities:

• Simulated both accurate and approximate MAC units using testbenches.

• Generated waveforms to observe signal behavior (input/output, done signal).

• Compared outputs across multiple test vectors.

• Calculated absolute error and accuracy rate for approximate modules.

🔸 Results Visualization:

🔸 Objective:

      To evaluate the hardware cost of the accurate and approximate DSP modules after synthesis in terms of area, power, and timing.

🔸 Key Activities:

• Synthesized the RTL design using a standard-cell library.

• Analyzed post-synthesis reports for:

  • Area (µm²)

  • Power consumption (mW)

  • Timing delay (ns)

  • Cell count

🔸 Results Visualization :