Project Mission
Project Mission
Embedded Files
This project focuses on designing a low-power DSP module—specifically a MAC unit—using approximate adders. Approximate adders reduce power, area, and delay by allowing small errors in computation, which is acceptable in many DSP applications like audio, image, and ML. The goal is to compare a standard and an approximate MAC unit at the RTL level using Cadence tools, analyzing the trade-off between accuracy and efficiency .
Stages of project
Stages of project
Stage 1
Stage 1
Selection of project
The project is selected based on its relevance to current VLSI design challenges and its feasibility using available tools and technologies
Stage 2
Stage 2
Design and Verification
Design and verification involve creating a functional VLSI system and ensuring its correctness through simulation and testing.
Stage 3
Stage 3
Netlist Generation
Netlist generation is the process of converting a VLSI circuit design into a list of electronic components and their interconnections.
Stage 4
Stage 4
Synthesized Design
A synthesized design in ASIC refers to the RTL code translated into an optimized gate-level netlist using standard cell libraries, ready for physical design and fabrication.
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