Journals
Design and Implementation of Gray-Coded Bit-Plane based Reconfigurable Motion Estimation Architecture Using Binary Content Addressable Memory for Video Encoder of an Efficient Multi-Pattern Motion Estimation Search Algorithm for HEVC/H.265. DOI: 10.1109/TCE.2021.3139944
Design and Implementation of an Efficient Multi-Pattern Motion Estimation Search Algorithm for HEVC/H.265. DOI: 10.1109/TCE.2021.3126670
A hybrid hardware oriented motion estimation algorithm for HEVC/H.265. DOI: 10.1007/s11554-020-01056-w
Design and Implementation of Efficient Streaming Deblocking and SAO Filter for HEVC Decoder. DOI: 10.1109/TCE.2018.2812518
Implementation and validation of quadral-duty digital PWM to develop a cost-optimized ASIC for BLDC motor drive . DOI: 10.1016/j.conengprac.2021.104752
Development of a cost‐effective circuit hardware architecture for brushless direct current motor driver. DOI: 10.1002/cta.3011
Conferences
A Motion Estimation Search Algorithm and its Hardware Implementation for HEVC/H.265. DOI: 10.1109/ICCE-Berlin50680.2020.9352198
A Hybrid Motion Estimation Search Algorithm for HEVC/H.265. DOI: 10.1109/iSES47678.2019.00037
Design and Implementation of low power 4 × 4/8 × 8 2D-DTT architecture for image and video compression. DOI: 10.1109/WITCONECE48374.2019.9092937