ABOUT ME
I am currently working as a Video CODEC Hardware Developer in the Multimedia team at Qualcomm India Pvt. Ltd. I completed my Ph.D in Electronics and Communication Engineering from National Institute of Technology, Meghalaya, India. Before that, I earned my M.Tech from National Institute of Technology, Nagaland, and B.E from Priyadarshini J.L. College of Engineering, Nagpur, Maharastra. Presently I am working on the development of high-performance hardware architectures for the Video CODEC standards like AV1, VVC (H.266) for the next generation SNAPDRAGON Chipsets. In my Ph.D, I worked on the development of Hardware-Oriented Optimized Motion Estimation Algorithms for HEVC (H.265) standard. The aim of the work was to reduce the Hardware Cost of the Inter-Prediction Engine by reducing the complexity of the Search Algorithms without sacrificing the video quality.