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Design Technology Co-Optimization (DTCO) [2021 - ]
Design Technology Co-Optimization (DTCO) [2021 - ]
In advanced logic technology development, traditional feature size scaling is no longer promising due to process challenges. Instead, DTCO (e.g., optimization of standard cell layout, BEOL stacks, backside PDN, and so on) is rising to extend CMOS scaling.
I evaluated and analyzed DTCO items in terms of block-level power, performance, and area (compared to the behaviors in ring oscillator circuits).
Thermal Analysis [2015 - 2018; 2022 - ]
Thermal Analysis [2015 - 2018; 2022 - ]
Thermal design power that constrains maximum performance of a processor should be accurately analyzed. However, its calculation in time and spatial domain is computationally expensive.
Electrothermal analogy has be proposed to simplify the calculation. I provided mathematical foundation of the analogy and expanded its boundary conditions for more precise analysis.
Smart Factory Solutions [2018 - 2020]
Smart Factory Solutions [2018 - 2020]
Smart factory collects manufacturing and inspection data to improve production yield and diagnose manufacturing equipment automatically.
I formulated equipment fault detection problem with product inspection data and implemented its solution with high accuracy.
Computational Lithography [2016 - 2018]
Computational Lithography [2016 - 2018]
Optical proximity correction (OPC), which is indispensable in nano-scale patterning, becomes more time-consuming due to more iterations of lithography simulation and denser patterns.
I proposed machine learning-guided OPC and light interference map-aware assist feature insertion to shorten mask synthesis runtime, still meeting its accuracy criteria.
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