Suhyeong Choi, Jinwook Jung, Andrew B. Kahng, Minsoo Kim, et. al., "PROBE3. 0: a systematic framework for design-technology pathfinding with improved design enablement," IEEE TCAD, 2023. [Link ]
Suhyeong Choi, Seongbo Shim, and Youngsoo Shin, "Neural network classifier-based OPC with imbalanced training data," IEEE TCAD, 2018. [Link]
Suhyeong Choi, Seongbo Shim, and Youngsoo Shin, "Electrothermal analysis with non-convective boundary conditions," IEEE TCAS-II, 2018. [Link]
Seongbo Shim, Suhyeong Choi, and Youngsoo Shin, "Light interference map: a prescriptive optimization of lithography-friendly layout," IEEE TSM, 2015. [Link]
Tathagata Srimani, Andrew Bechdolt, Suhyeong Choi, et al., "N3XT 3D Technology Foundations and Their Lab-to-Fab: Omni 3D Logic, Logic+ Memory Ultra-Dense 3D, 3D Thermal Scaffolding," IEDM, 2023. [Link ]
Carlo Gilardi, Gilad Zeevi, Suhyeong Choi, et al., "Barrier Booster for Remote Extension Doping and its DTCO for 1D & 2D FETs," IEDM, 2023. [Link ]
Seongbo Shim, Suhyeong Choi, and Youngsoo Shin, ”Machine learning-based 3D resist model,” SPIE Advanced Lithography, 2017. [Link]
Suhyeong Choi, Jae Uk Lee, Victor Blanco, Ryoung-Han Kim, and Youngsoo Shin, ”2D self-aligned via patterning strategy with EUV single exposure in 3nm technology,” SPIE Advanced Lithography, 2017. [Link]
Suhyeong Choi, Jae Uk Lee, Victor Blanco, Peter Debacker, Praveen Raghavan, Ryoung-Han Kim, and Youngsoo Shin, ”Large marginal 2D self-aligned via patterning for sub-5nm technology,” SPIE Advanced Lithography, 2017. [Link]
Kiwon Yoon, Suhyeong Choi, and Youngsoo Shin, ”Area efficient neuromorphic circuit based on stochastic computation,” ISOCC, 2016. [Link]
Seongbo Shim, Suhyeong Choi, and Youngsoo Shin, ”Machine learning (ML)-based lithography optimization,” APCCAS, 2016. [Link]
Suhyeong Choi, Seongbo Shim, and Youngsoo Shin, ”Machine learning (ML)-guided OPC using basis functions of polar Fourier transform,” SPIE Advanced Lithography, 2016. [Link]
Suhyeong Choi, Seongbo Shim, and Youngsoo Shin, ”Electrothermal analysis with generalized boundary conditions,” ISOCC, 2015. [Link]
Seongbo Shim, Suhyeong Choi, and Youngsoo Shin, ”Machine Learning for Mask Synthesis,” Machine Learning in VLSI Computer-Aided Design, Chapter 3, Springer, 2019. [Link]
Suhyeong Choi, et al., "Method for taper-free placement of standard cell within a integrated circuit design," 2022 (application/registration numbers: 18/156494 and 2022-0062828 in the US and Korea, respectively).
Suhyeong Choi, et al., "Placement methodology for power source tap cell (PTC) for back side-power delivery network (BS-PDN)," 2022 (application/registration numbers: 19/113133 and 2022-0061379 in the US and Korea, respectively).
Jong Myoung Lee, Suhyeong Choi, and Duk Young Lee, “Method and electronic apparatus for displaying inspection result of board,” 2019 (application/registration numbers: 16/624619, 19817118.3, 2019-0153629, and 201980003048.9 in the US, Europe, Korea, and China, respectively).
Jong Myoung Lee, Suhyeong Choi, and Duk Young Lee, “Method and electronic apparatus for determining cause of mounting failure for component mounted on board/substrate,” 2019 (application/registration numbers: 16/621142, 19812895.1, 2019-0077004, and 201980002555.0 in the US, Europe, Korea, and China, respectively).