• Served as Faculty Organizer / Co-convenor for “Riviera” an international cultural and sports fest between 2009 and 2019.

• Served as Faculty Organizer for “graVITas” an international technical fest between 2009 and 2012.

• Served as Assistant Chief Superintendent in Controller of Examination between 2008 and 2010.

• Served as Continuous Assessment Test Coordinator between 2009 and 2011, School of Electrical Sciences, VIT University, Vellore, Tamilnadu, India.

• Served as Coordinator for ABET accreditation visit during 2010 and 2014.

• Served as Coordinator for NAAC accreditation visit during 2010 and 2014.

• Organizing Committee Member for the Silver Jubilee Conference on “Communication Technologies and VLSI Design” (CommV’09) conducted by VIT University, Vellore, Tamilnadu India held during 6th to 10th October 2009.

• Organizing Committee Member for the International Conference on “Sensors and Related Networks” (SENNET’09) conducted by VIT University, Vellore, Tamilnadu India held during 8th to 10th December 2009.

• Served as Rapporteur for the International Conference on “Advances in Electrical Engineering” (ICAEE’14) conducted by VIT University, Vellore, Tamilnadu India held during 8th to 10th December 2009.

• Organizing Committee Member for “Engineers Day” conducted by VIT University, Vellore, Tamilnadu India held during 2015 and 2016.

1. Workshop on “Digital ASIC Design Flow and FPGA Implementation” at VIT University, Vellore, Tamilnadu, India between 11th and 15th June 2007.

2. Hands-on Training Programme on “Advanced FPGA based System Design” at VIT University, Vellore, Tamilnadu, India between 4th and 18th July 2007.

3. Faculty development program on “FPGA based System Design using ALTERA EDA Tools” at VIT University, Vellore, Tamilnadu, India between 29th and 30th August 2008.

4. Training Programme on "PSoC Designer" at VIT University, Vellore, Tamilnadu, India between  7th March 2010.

5. Hands on Training Programme “FPGA Based System Design using ALTERA EDA Tool” at VIT University, Vellore, Tamilnadu, India between 29th and 31st October 2010.

6. Training Programme on “FPGA Based System Design using ALTERA EDA Tool” at VIT University, Tamilnadu, Vellore, India on 15th and 16th October 2011.

7. Faculty development program on “Digital, Analog & Mixed Signal IC Design using CADENCE EDA Tool” at VIT University, Vellore, Tamilnadu, India between 3rd and 5th  September 2014.

8. Faculty development program on “Simulation of Nanoscale Devices using Synopsys TCAD” at VIT University, Vellore, Tamilnadu, India between 16 and 17th September 2014.

9. Workshop on “Hands on Practical Electronics for School Student” at VIT University, Vellore, Tamilnadu, India between 18th and 22nd May 2015.

10.  Workshop on “Simulation of Nanoscale Devices using Synopsys TCAD” at VIT University, Vellore, and Tamilnadu, India on 22nd   September 2015.

11. Hands on training program on “FPGA Based System Design Using QSYS & NIOS II” at VIT University, Vellore, Tamilnadu, India between 2nd   and 3rd October   2015.

12. Hands on training programme on “Digital IC Design Flow Using Synopsys IC Bundle at VIT University, Vellore, Tamilnadu, India between 7th and 9th October 2015.

13. Hands on training program on “FPGA Based System Design Using QSYS & NIOS II” at VIT University, Vellore, Tamilnadu, India between 19th   and 20th March  2016.

14. Webinar on “Device Simulation using Visual TCAD” at VIT University, Vellore, Tamilnadu, India on 7th September 2016.

15. IEEE Mini Colloquium on “Emerging Trends in Electronic Systems” at VIT University, Tamilnadu between 14th and 15th October 2016.

16. Mini Colloquium on “Nanofabrication Technologies” at VIT University, Tamilnadu between 4th and 5th November 2016.

17. Alumni Meet “VLSI Technical Alumni Meet” at Bengaluru for M.Tech VLSI Design Alumni on 25th February 2017.

18. Training Programme on “SKILL using Cadence EDA Tool” at VIT University, Tamilnadu between 25th March 2017.

19. International Conference on Microelectronic Devices, Circuits and Systems” at VIT University, Vellore, Tamilnadu, India between 10th to 12th August 2017.

20. Value Added Programme on “FPGA Based System Design Using Intel FPGA” at VIT University, Vellore, Tamilnadu, India on 3rd February 2018.

21. Value Added Programme on “FPGA Based System Design Using Intel FPGA” at VIT University, Vellore, Tamilnadu, India on 10th  February 2018.

22. Alumni Meet “VLSI Technical Alumni Meet” at Bengaluru for M.Tech VLSI Design Alumni on 10th March 2018..

23. Value Added Programme on “FPGA Based System Design Using Intel FPGA” at VIT University, Vellore, Tamilnadu, India on 17th  March 2018.

24. Value Added Programme on “System Integration using Intel Quartus Prime” at VIT University, Vellore, Tamilnadu, India on 18th  March 2018.

25. Value Added Programme on “FPGA Based System Design Using Intel FPGA” at VIT University, Vellore, Tamilnadu, India on 25th  August 2018.

26. Alumni Meet “VLSI Technical Alumni Meet” at Bengaluru for M.Tech VLSI Design Alumni on 9th March 2019..

27. Hands on training programme on “Basic Intel FPGA Design” at VIT University, Vellore, Tamilnadu, India between 14th   and 15th September  2019.

28. International Conference on Microelectronic Devices, Circuits and Systems” at VIT University, Vellore, Tamilnadu, India between 11h to 13th  February 2021.

29. Virtual Workshop  on “System Verilog and High Level Synthesis” at VIT University, Vellore, Tamilnadu, India between 6th   and 7h December 2021.

1.  “FPGA and its Applications” at National Level Seminar on " VLSI Application in Power Electronics" organized by Department of EEE, Kings College of Engineering, Pudukottai held on 23rd August 2008.

2.  “FPGA and its Applications” at National Level Seminar on " VLSI Design Flow & Applications" organized by Department of EEE, Kumaraguru College of Technology, Coimbatore held on 4th  August 2008.

3. “Verilog HDL Programming” at VIT University organized by Instrument Society of India, VIT University held on 11th October 2008.

4. “Trends in VLSI” at VIT University organized by IET Student Chapter, VIT University held on 10th March 2009.

5. “Verilog HDL Coding and FPGA Implementation ” at Summer Camp on Programming for Electronics Engineer organized by Embedded Division, SENSE, VIT University held between 24.06.2010  and 29.06.2010.

6.  “FPGA Based System Design” at National Level workshop on “VLSI Design" organized by Department of ECE, Sri Balaji Chockalingam Engineering College, Arni, Tamilnadu held on 18th & 19th February 2012.

7. “System Design using Nanoscale CMOS” at Faculty development program on "CMOS Technologies Design and Implementation " organized by Department of ECE, Angel College of Engineering and Technology, Tirupur, Tamilnadu held on 28th & 29th June 2012.

8. “Linear Integrated Circuits” at Faculty development program sponsored by Anna University organized by Department of ECE, SKP Engineering College, Thiruvannamalai, Tamilnadu held on 14th June 2014.

9. “VLSI Design”  Special Lecture organized by Department of ECE, M.Kumarasamy College of Engineering, Karur, Tamilnadu held on 23rd February 2019.

1. Participated in 10 days faculty Enrichment Programme in GLOBALFOUNDRIES, Bangalore from 05.12.2016 to 15.12.2016.

Area: RF Compact Modelling, Self-Heating in MOS Device and RF Perspective and Process variation study on FD SOI MOSFET.

2. Participated in Immersion in Skill Development Methodologies at Infineon, Melaka. Malaysia from 21.08.2018 to 24.08.2018.

Area: Exposure to Automotive Chip Fab and Testing Unit

• • Two days training programme on “Synopsys Sentarus TCAD Tools” Organized by Nanochip Solutions, Bengaluru on 5th and 6th March 2018.

• • Three Days training programme on “Design Compiler – RTL Synthesis”, Organized by Synopsys, Bengaluru, 20th  to 22nd March 2019.

• • Three Days training programme on “ICC2 – Block Level Implementation”, Organized by Synopsys, Bengaluru, 4th   to 6th  March  2020.