Research Areas

• • System Validation

  • Hardware Security

  • Novel Interconnect Design (NoC, WNoC)

System Validation

The huge time requirement for the thorough validation of complex integrated circuits using extensive simulation and formal verification in the pre-silicon stage is unbearable and introduces the threat of missing the time to market. This has encouraged the silicon debug technique to find out the undetected design bugs as soon as the first silicon is available. Silicon debug includes two steps known as (i) data acquisition and (ii) analysis. The major challenges in the silicon debug data acquisition stage can be primarily faced at two levels as follows: (i) Storing the huge trace data (limited trace buffer size), (ii) Low bandwidth off-chip interface to transfer the sampled trace data. Moreover, the debug structure becomes vestigial once the product validation phase is over. In this context, my PhD work proposes a wireless-enabled debug structure for faster trace communication, a redundant trace elimination mechanism for efficient trace reduction and reuse of trace buffer as routers’ virtual channel for system performance improvement.

Hardware Security

The third-party IP blocks integrated together with other system modules can introduce various security attacks through the shared resources to degrade system performance. A Denial-of-Service (DoS) attack in a network is an attack that diminishes a network’s ability to provide appropriate services to legitimate users. A malicious third-party IP can trigger a DoS attack by either injecting useless packets on the NoC or holding the shared NoC resources. As a result, the network exhibits increased communication latency, leading to the unavailability of the NoC for other legitimate on-chip modules. Therefore, it is of utmost importance to accurately detect DoS attacks at an early stage and prevent the system from severe performance degradation. Once an attack is detected, the source of the attack needs to be localized and appropriate actions need to be taken to restore the system to a healthy state.

Novel Interconnect Design (NoC, WNoC)

Network-on-Chip (NoC) is popularly accepted as the scalable medium for connecting multiple cores on modern System-on-Chips (SoC). To improve the performance of on-chip long-distance communication, Wireless NoC (WNoC) has emerged as a radical solution. Despite its various advantages, power consumption in NoC has been a major limiter. Moreover, WNoC treats all WIs equally and all the packets taking the wireless path equally, which leads to inefficient wireless resource utilization and system performance degradation. In this context, we propose a dynamic power control framework for VC power management in NoC, and a channel access mechanism for WNoC that prioritizes the critical data on the network.