Publications

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Book Chapter:

1. 1. Mitali Sinha, Sidhartha Sankar Rout, Sujay Deb, "DoS Attack Models and Mitigation Frameworks for NoC-based SoCs", in Electronic Design for AI, IoT and Hardware Security, Frontiers of Electronic Design, ISQEDFED, Publisher: Springer, 2022. [Accepted]

   2. Sidhartha Sankar Rout, Mitali Sinha, Sujay Deb, "NoC Post-Silicon Validation and Debug", in Network-on-Chip Security and Privacy, Springer Nature, 2021, ISBN 978-3-030-69131-8. [ DOI ]

Journal:

1. 1. Sidhartha Sankar Rout, Mitali Sinha, Sujay Deb, "2DMAC: A Sustainable and Efficient Medium Access Control Mechanism for Future Wireless NoCs", in ACM Journal on Emerging Technologies in Computing Systems (ACM JETC). [Under Review]

   2. Sidhartha Sankar Rout, M Badri, Mitali Sinha, Sujay Deb, "ReDeSIGN: Reuse of Debug Structures for Improvement in Performance Gain of NoC based MPSoCs", in IEEE Transactions on Emerging Topics in Computing (IEEE TETC). [Under Review]

   3. Mitali Sinha, Setu Gupta, Sidhartha Sankar Rout, Sujay Deb, "Sniffer: A Machine Learning Approach for DoS Attack Localization in NoC-based SoCs", in IEEE Journal on Emerging and Selected Topics in Circuits and Systems (IEEE JETCAS). [DOI]

   4. Mitali Sinha, Pramit Bhattacharyya, Sidhartha Sankar Rout, Neha Bhairavi Prakriya, Sujay Deb, "Securing an Accelerator-rich System from Flooding-based Denial-of-Service Attacks", in IEEE Transactions on Emerging Topics in Computing (IEEE TETC). [ DOI ]

   5. Sidhartha Sankar Rout, Sujay Deb, Kanad Basu, "WiND: An Efficient Post-Silicon Debug Strategy for Network-on-Chip", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD). [ DOI ]

Peer-reviewed Conferences:

1. 1. Sidhartha Sankar Rout, Akshat Singh, Suyog Bhimrao Patil, Mitali Sinha, Sujay Deb, "Security Threats in Channel Access Mechanism of Wireless NoC and Efficient Countermeasures", in the Proc. IEEE International Symposium on Circuits and Systems (ISCAS) 2020, Seville, Spain. [ DOI | Poster | Presentation | Video ]

   2. Sidhartha Sankar Rout, Badri M, Sujay Deb, "Reutilization of Trace Buffers for Performance Enhancement of NoC based MPSoCs", in the Proc. 25th Asia and South Pacific Design Automation Conference (ASP-DAC) 2020, Beijing, China. [ DOI | Presentation ]

   3. Priyanshi Gaur, Sidhartha Sankar Rout, Sujay Deb, "Efficient Hardware Verification Using Machine Learning Approach", in the Proc. 5th IEEE International Symposium on Smart Electronic Systems (IEEE-iSES, formerly IEEE-iNIS) 2019, Rourkela, India. [ DOI | Presentation ]

   4. Sidhartha Sankar Rout, Vaibhav Ishwarlal Chaudhari, Suyog Bhimrao Patil, Sujay Deb, "RCAS: Critical Load Based Ranking for Efficient Channel Allocation in Wireless NoC", in the Proc. 32nd IEEE International System-on-Chip Conference (SOCC) 2019, Singapore. [ DOI | Presentation ]

   5. Sidhartha Sankar Rout, Suyog Bhimrao Patil, Vaibhav Ishwarlal Chaudhari, Sujay Deb, "Efficient Router Architecture for Trace Reduction During NoC Post-Silicon Validation", in the Proc. 32nd IEEE International System-on-Chip Conference (SOCC) 2019, Singapore. [ DOI | Poster]

   6. Sidhartha Sankar Rout, Kanad Basu, Sujay Deb, "Efficient Post-Silicon Validation of Network-on-Chip using Wireless Links", in the Proc. 32nd International Conference on VLSI Design (VLSID) 2019, Delhi, India. [ DOI | Presentation ]

   7. Mitali Sinha, Sidhartha Sankar Rout, Sri Harsha Gade, Sujay Deb, "Near Threshold Last Level Cache for Energy Efficient Embedded Applications", in the Proc. 9th International Green and Sustainable Computing Conference (IGSC) 2018, Pittsburgh, USA. [ DOI ]

   8. Sri Harsha Gade, Sidhartha Sankar Rout, Sujay Deb, “On-Chip Wireless Channel Propagation: Impact of Antenna Directionality and Placement on Channel Performance”, in the Proc. 12th IEEE/ACM International Symposium on Networks-on-Chip (NOCS) 2018, Torino, Italy. [ DOI ]

   9. Sri Harsha Gade, Sidhartha Sankar Rout, Ravi Kashyap, Sujay Deb, "Reliability Analysis of On-Chip Wireless Links for Many Core WNoCs", in the Proc. 33^rd conference on Design of Circuits and Integrated Systems (DCIS) 2018, Lyon, France.[ DOI ]

   10. Ravi Kashyap, Twinkle Verma, Priyanka Kwatra, Sidhartha Sankar Rout, "Efficient Data Compression Scheme for Secured Application Needs", in the Proc. 22^nd International Symposium on VLSI Design and Test (VDAT) 2018, Madurai, India.[ DOI ]

   11. Sri Harsha Gade, Mitali Sinha, Sidhartha Sankar Rout, and Sujay Deb, "Enabling Reliable High Throughput On-Chip Wireless Communication for Many Core Architectures", in the Proc. IEEE International Symposium on VLSI (ISVLSI) 2018, Hong Kong SAR, China. [ DOI ]

   12. Sri Harsha Gade, Sidhartha Sankar Rout, Mitali Sinha, Hemanta Kumar Mondal, Wazir Singh, and Sujay Deb, "A Utilization Aware Robust Channel Access Mechanism for Wireless NoCs", in the Proc. IEEE International Symposium on Circuits and Systems (ISCAS) 2018, Florence, Italy. [ DOI ]

   13. Sidhartha Sankar Rout, Hemanta Kumar Mondal, Rohan Juneja, Sri Harsha Gade and Sujay Deb, "Dynamic NoC Platfrom for Varied Application Needs", in the Proc. The 19^th International Symposium on Quality Electronic Design (ISQED), pp. 232-237, March 2018, Santa Clara, USA. [ DOI | Poster ]

   14. Abhay Kumar, Sidhartha Sankar Rout, Varun Goel, "Speech Mel Frequency Cepstral Coefficient feature classification using multi level support vector machine", in the Proc. 4^th IEEE UP Section International Conference on Electrical, Computer and Electronics (UPCON), pp. 134-138, October 2017, Mathura, India. [ DOI ]

   15. Varun Goel, Abhay Kumar, Sidhartha Sankar Rout, Anuj Kr Maurya, Sanjay Sharma, Sanjay Kumar, "2-D analytical model of surface potential for graded-channel-double-gate (GCDG) MOSFETs", in the Proc. 3^rd International Conference on Signal Processing and Communication (ICSC), pp. 448-451, December 2016, Noida, India. [ DOI ]

   16. Deepak Baranwal, Digvijay Singh, Khanusiya Soyeb, Sidhartha Sankar Rout, Sujay Deb, "Reliability Enhancement of SoCs Based on Dynamic Memory Access Profiling in Conjunction with PVT Monitoring", in the Proc. 28^th International Conference on VLSI Design (VLSID), pp. 541-546, January 2015, Bangalore, India. [ DOI ]

Patent:

1. 1. Sidhartha Sankar Rout, Sujay Deb, "Method and System for Post Silicon Validation", Application Number: 201911006527, filed on :19/02/2019, published on: 21/08/2020. (Indian Patent)

Thesis:

1. 1. Sidhartha Sankar Rout, "Reliability Aware Intelligent Memory Management (RAIMM)", M.Tech Thesis, 2012. [Thesis pdf]

Award:

1. 1. Sidhartha Sankar Rout,"Efficient Post-Silicon Debug Platforms for Future Many-Core Systems", VLSID 2021 Student Research Forum First Prize. [Presentation] [Award Certificate]

   2. Sidhartha Sankar Rout, "Security Threats in Channel Access Mechanism of Wireless NoC and Efficient Countermeasures " IVPC 2020 Third Prize. [Magazine Article | Presentation] [Award Certificate]

   3. Sidhartha Sankar Rout, "Efficient Post-Silicon Debug Framework for Network-on-Chip", ASP-DAC 2021 Student Research Forum Best Poster Award - Most Popular. [Poster | Short Presentation | Long Presentation] [Award Certificate]

   4. Sidhartha Sankar Rout, "Efficient Post-Silicon Debug Platforms for Future Many-Core Systems", DST AWSAR Award, 2019. [Article PDF] [Award Certificate]