Research Work

Research Interests

1. Epitaxial growth of Si/Ge on epitaxial rare earth oxide for logic application

2. Advanced devices (SOI MOSFET, FinFET, and NSHFET): Characterization, Simulation, and  Modeling

Reseach work

OHighly Oriented Crystalline Si on Epitaxial Gd2O3/Si (111) Substrate Using Low-Cost Rf Sputtering for Silicon on Insulator Application, 

Silicon-on-Insulator (SOI) technology has been the center of attraction with the advancement in Radio Frequency (RF) technology and the advent of Internet-of-Things due to its low-power operation with reduced parasitic and short-channel effects. However, the state-of-the-art smart-cut method used for the SOI wafer is costly. Alternatively, the notion of using the Si channel layer on epitaxial rare-earth oxide has been proposed. In literature, the existing techniques used to achieve the same, such as Molecular beam Epitaxy or reduced-pressure chemical vapor deposition technique, are either costly or non-high-volume manufacturable. In this context, we propose a method to fabricate the highly oriented crystalline Si(111) channel layer (Top-Si) on an epitaxial Gd2O3/Si(111) virtual substrate (SOXI) utilizing the solid phase epitaxy using the high-volume manufacturing-friendly (HVM), low-cost RF magnetron sputtering technique. First, we have shown the multi-crystalline Si and epitaxial Gd2O3 layer grown on Si(111) substrate, as confirmed using high-resolution X-ray diffraction (HRXRD) and Transmission Electron Microscopy (TEM). Second, we investigated the impact of rapid thermal annealing at 850 °C on the heterostructure using HRXRD and TEM. It is observed that the high-temperature annealing transforms the Top-Si layer into the highly oriented crystalline Si(111) layer by fusing smaller grains towards larger grains. Hence, we demonstrate a low-cost, HVM-friendly technique for the fabrication of SOXI wafers. 

Process Voltage Temperature Variability Estimation of Tunneling Current for Band-to-Band-Tunneling based Neuron 

Compact and energy-efficient synapse and neurons are essential to realize the full potential of neuromorphic computing. In addition, a low variability is indeed needed for neurons in deep neural networks for higher accuracy. Further, process (P), voltage (V), and temperature (T) (PVT) variation are essential considerations for low-power circuits as performance impact and compensation complexities are added costs. Recently, band-to-band tunneling (BTBT) neuron has been demonstrated to operate successfully in a network to enable a liquid state machine (LSM). A comparison of the PVT with competing modes of operation (e.g., BTBT versus subthreshold and above threshold) of the same transistor is a critical factor in assessing performance. In this work, we demonstrate the PVT variation impact on the BTBT regime and benchmark the operation against the subthreshold regime (SS) and ON-regime ( ION ) of partially depleted silicon-on-insulator MOSFET. It is shown that the ON-state regime offers the lowest variability but dissipates higher power, hence not usable for low-power sources. Among the BTBT and SS regimes, which can enable the low-power neuron, the BTBT regime has shown ∼3× variability reduction ( σID/μID ) compared to the SS regime, considering the cumulative PVT variability. The improvement is due to the well-known weaker P, V, and T dependence of BTBT versus SS. We show that the BTBT variation is uncorrelated with mutually correlated SS and ION operation—indicating its different origin from the mechanism and location perspectives. Hence, the BTBT regime is promising for low-current, low-power, and low device-to-device (D2D) variability neuron operation.

Schottky Barrier MOSFET Enabled Ultra-Low Power Real-Time Neuron for Neuromorphic Computing 

Energy-efficient real-time synapses and neurons are essential to enable large-scale neuromorphic computing. In this work, we propose and demonstrate the Schottky-Barrier MOSFET-based ultra-low power voltage-controlled current source to enable real-time neurons for neuromorphic computing. Schottky-Barrier MOSFET is fabricated on a Silicon-on-insulator (SOI) platform with polycrystalline Silicon as the channel and Nickel/Platinum as the source/drain. The Poly-Si and Nickel make the back-to-back Schottky junction enabling ultra-low ON current required for energy-efficient neurons. 

Phase evolution in epitaxial Gd2O3 due to anneal temperature for silicon on insulator application

Epitaxial growth of Si on rare-earth oxides on Si wafer using sputter technology promises cheaper and high-volume manufacturing of Silicon-on-insulator (SOI) wafers over costly solutions like the smart-cut method. Further, rapid thermal annealing (RTA) in standard complementary metal–oxide–semiconductor (CMOS) processing affects the performance of SOI substrate through chemical and crystal phase change. Herein, we present a systematic study on the rich physical and chemical phase evolution of epitaxial Gd2O3 grown on Si (111) using RF sputtering subjected to RTA temperatures (850 − 1050 °C). First, X-ray diffraction analysis shows a significant enhancement of the epitaxial cubic phase in as-deposited Gd2O3 at an optimum RTA temperature of 850 °C, which is partially explained by epitaxial-regrowth of an amorphous layer at Gd2O3/Si interface as observed in Transmission Electron Microscopy. Secondly, the degradation of crystallinity beyond 900 °C is correlated with temperature-dependent Si diffusion into Gd2O3 that becomes observable by X-ray photoelectron spectroscopy. The Gd2O3 crystallinity is completely quenched into the amorphous gadolinium silicate phase at 1050 °C. Eventually, we employed X-ray reflectivity modeling to evaluate the film thickness variation with RTA. This study provides a detailed insight into the structural and chemical dynamics occurring in epitaxial-Gd2O3 film for CMOS-relevant temperatures. 

Process-Induced Variability-Aware Compact Model-Based Circuit Performance Estimation for Design-Technology Co-Optimization 

In sub-10-nm fin field-effect transistors (FinFETs), line-edge roughness (LER) and metal-gate granularity (MGG) are the two most dominant sources of variability and are mostly modeled semi-empirically. In this work, compact models of LER and MGG are used. We show an accurate process-induced variability (PIV)-aware compact model-based circuit performance estimation for design-technology co-optimization (DTCO). This work is carried out using an experimentally validated Berkeley Short-channel IGFET Model–Common MultiGate (BSIM-CMG) model on a 7-nm FinFET node. First, we have shown performance benchmarking of LER and MGG models with the state of the art and shown ∼4× (∼2.3×) accuracy improvement for nMOS (pMOS) in the estimation of device figure of merits (DFoMs). Second, ring oscillator (RO) and static random-access memory (SRAM) circuit’s performance estimation is carried out for LER and MGG variability. Furthermore, ∼22% more optimistic estimate of (σ /μ)SHM (static hold margin) compared to the state-of-the-art model with VDD variation is shown. Finally, we demonstrate our improved DFoM accuracy translated to more accurate circuit figure of merits (CFoMs) performance estimation. For worst-case SHM (3(σ /μ)SHM@VDD = 0.75 V) compared to state of the art, dynamic (standby) power reduction by ∼73% (∼61%) is shown. Thus, our enhanced variability model accuracy enables more credible DTCO with significantly better performance estimates. 

Modelling of channel doping gradient (CDG) LDMOS transistors based on HiSIM-HV2 model 

A physics-based parameter extraction methodology based on HiSIM-HV2 model is developed to capture the effect of CDG on the performance of LDMOS transistors. The CDG shows up to 30% performance benefit. The physics behind this is investigated using TCAD simulations and the learning from the simulations is used to efficiently extract the model parameters. The spice simulations with extracted parameters further confirm advantage of CDG on circuit performance.