Hello! I'm an assistant professor in the department of electrical engineering at Kyung Hee University (Mar. 2023~). Before joining Kyung Hee University, I was a postdoctoral researcher at University of Michigan (MICL group) working on high-performance digital signal processing hardware design.
I received my PH.D. degree in Electrical Engineering from Korea Advanced Institute of Science and Technology (KAIST) under the supervision of Prof. Lee-Sup Kim.
My detailed research interest includes:
VLSI implementation of high-performance and energy-efficient hardware accelerators
On-device reconfigurable architecture for deep neural networks
Algorithm/hardware co-design for next-generation intelligent systems
Contact (email): seungkc at khu dot ac dot kr
Experience
Mar. 2023 - Present Assistant Professor in the department of EE at Kyung Hee University, South Korea
Mar. 2022 - Feb. 2023 Postdoctoral Associate at University of Michigan, Ann Arbor, MI, USA (PI: Prof. Hun-Seok Kim)
Mar. 2016 - Feb. 2022 Graduate Student Researcher at KAIST, Daejeon, South Korea
- Served as a student representative in MVLSI Lab. (2020) and a teaching assistant for Digital System / Digital Integrated Circuits (2017-2020)
Jun. 2015 - Aug. 2015 Summer Internship at SK Hynix, Icheon, South Korea
Education
Mar. 2018 ~ Feb. 2022
Ph.D. in School of Electrical Engineering, KAIST, Daejeon, South Korea
Mar. 2016 ~ Feb. 2018
M.S. in School of Electrical Engineering, KAIST, Daejeon, South Korea
Feb. 2011 ~ Feb. 2016
B.S. in School of Electrical Engineering, KAIST, Daejeon, South Korea (Cum Laude)
Mar. 2009 ~ Feb. 2011
High school diploma in D(T)aegu Science High School (completed in two years)
Publications
International Conference Papers
ParaBase: A Configurable Parallel Baseband Processor for Ultra-High-Speed Inter-Satellite Optical Communications
Seungkyu Choi, Huanshihong Deng, Kuan-Yu Chen, Yufan Yue, David Blaauw, and Hun-Seok Kim
IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2024 (Accepted)
MERSIT: A Hardware-Efficient 8-bit Data Format with Enhanced Post-Training Quantization DNN Accuracy
Nguyen-Dong Ho, Gyujun Jeong, Cheol-Min Kang, Seungkyu Choi* and Ik Joon Chang*
ACM/IEEE Design Automation Conference (DAC), 2024 (Accepted)
SONA: An Accelerator for Transform-Domain Neural Networks with Sparse-Orthogonal Weights
Pierre Abillama, Zichen Fan, Yu Chen, Hyochan An, Qirui Zhang, Seungkyu Choi, David Blaauw, Dennis Sylvester, and Hun-Seok Kim
IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), 2023 (Best Paper Nominee)
Algorithm/Architecture Co-Design for Energy-Efficient Acceleration of Multi-Task DNN
Jaekang Shin, Seungkyu Choi, Jongwoo Ra, and Lee-Sup Kim
ACM/IEEE Design Automation Conference (DAC), 2022 [DOI]
A Convergence Monitoring Method for DNN Training of On-device Task Adaptation
Seungkyu Choi, Jaekang Shin, and Lee-Sup Kim
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2021 [DOI]
A Pragmatic Approach to On-device Incremental Learning System with Selective Weight Updates
Jaekang Shin, Seungkyu Choi, Yeongjae Choi, and Lee-Sup Kim
ACM/IEEE Design Automation Conference (DAC), 2020 [DOI]
A 47.4µJ/epoch Trainable Deep Convolutional Neural Network Accelerator for In-Situ Personalization on Smart Devices
Seungkyu Choi, Jaehyeong Sim, Myeonggu Kang, Yeongjae Choi, Hyeonuk Kim, and Lee-Sup Kim
IEEE Asian Solid-State Circuits Conference (A-SSCC), 2019 [DOI]
Compressing Sparse Ternary Weight Convolutional Neural Networks for Efficient Hardware Acceleration
Hyeonwook Wi, Hyeonuk Kim, Seungkyu Choi, and Lee-Sup Kim
IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2019 [DOI]
An Optimized Design Technique of Low-bit Neural Network Training for Personalization on IoT Devices
Seungkyu Choi, Jaekang Shin, Yeongjae Choi, and Lee-Sup Kim
ACM/IEEE Design Automation Conference (DAC), 2019 [DOI]
TrainWare: A Memory Optimized Weight Update Architecture for On-Device Convolutional Neural Network Training
Seungkyu Choi, Jaehyeong Sim, Myeonggu Kang, and Lee-Sup Kim
IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2018 [DOI]
SENIN: An Energy-efficient Sparse Neuromorphic System with On-chip Learning
Myung-Hoon Choi, Seungkyu Choi, Jaehyeong Sim, and Lee-Sup Kim
IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2017 [DOI]
International Journal Papers
Accelerating On-Device DNN Training Workloads via Runtime Convergence Monitor
Seungkyu Choi, Jaekang Shin, and Lee-Sup Kim
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, May 2023 [DOI]
Energy-Efficient CNN Personalized Training by Adaptive Data Reformation
Youngbeom Jung, Hyeonuk Kim, Seungkyu Choi, Jaekang Shin, and Lee-Sup Kim
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jan. 2023 [DOI]
A Deep Neural Network Training Architecture with Inference-aware Heterogeneous Data-type
Seungkyu Choi, Jaekang Shin, and Lee-Sup Kim
IEEE Transactions on Computers, May 2022 [DOI]
Rare Computing: Removing Redundant Multiplications from Sparse and Repetitive Data in Deep Neural Networks
Kangkyu Park, Seungkyu Choi, Yeongjae Choi, and Lee-Sup Kim
IEEE Transactions on Computers, Apr. 2022 [DOI]
An Energy-Efficient Deep Convolutional Neural Network Training Accelerator for In Situ Personalization on Smart Devices
Seungkyu Choi, Jaehyeong Sim, Myeonggu Kang, Yeongjae Choi, Hyeonuk Kim, and Lee-Sup Kim
IEEE Journal of Solid-State Circuits, Oct. 2020 [DOI]
Energy-Efficient Design of Processing Element for Convolutional Neural Network
Yeongjae Choi, Dongmyung Bae, Jaehyeong Sim, Seungkyu Choi, Minhye Kim, and Lee-Sup Kim
IEEE Transactions on Circuits and Systems II, Nov. 2017 [DOI]
Patents
International
Method and Apparatus with Neural Network Compression (US-17892481)
Method and Device for Encoding (US-17401453)
Method and Apparatus with Incremental Learning Model (US-17089764; CN-202110055314.1)
Method and Apparatus with Neural Network Data Quantizing (US-15931362; EP-20183579; CN-202011086791.6)
Domestic
Processing Unit for Processing Multi-Tasks (KR-10-2021-0143670)
Method and Apparatus for Compressing a Neural Network (KR-10-2021-0143629)
Exponent Encoded Half-float Representation for Enabling Brick-level Fixed-point MAC (KR-10-2021-0028929)
Method of Binary Mask (KR-10-2020-0041638)
Local Maximum Quantization for Convolutional Neural Network Training (KR-10-2019-0126298)
Honors/Awards
IDEC Congress Chip Design Contest 2019 Best Poster Award
Main recipient, "A Deep Convolutional Neural Network Training Processor for Personalization on Smart Devices"
KAIST Bachelor's Degree Cum Laude
Korea Government Full Scholarship (KAIST)
Academic Services
Reviewer
IEEE Transactions on Circuits and Systems I (TCAS-I): 2019, 2021, 2022, 2023
IEEE Transactions on Circuits and Systems II (TCAS-II): 2022
IEEE Open Journal of Circuits and Systems (OJCAS): 2020
IEEE Open Journal of the Solid-State Circuits Society (OJSSCS): 2021
IEEE Transactions on Emerging Topics in Computing (TETC): 2021, 2023
IEEE Transactions on Magnetics: 2022