• VLSI implementation of high-performance, energy-efficient domain-specific processors (Especially AI hardware design)

• Reconfigurable computer architecture study

• Software(+algorithm)/hardware co-design for next-generation intelligent systems

• 2025/07/28 - Our group's paper "Accelerating On-Device Visual Task Adaptation by Exploiting Hybrid Sparsity in DNN Training" has been accepted to Journal of Systems Architecture. Congratulations Minje and Yeonsik!

• 2025/06/24 - Three of our group's papers are presented at Summer Annual Conference of IEIE, 2025. Congratulations Junyoung, Yeonsik and Soomin!

• 2024/03/01 - Junyoung, Yeonsik, Jiyun, Hyeonseong and Myeongjin have joined our group as graduate researchers. Welcome.

• 2025/02/16 - Our group's paper "Precon: A Precision-Convertible Architecture for Accelerating Quantized Deep Learning Models across Various Domains Including LLMs" has been accepted to DAC'25. Congratulations Jongwoo, Hyeonseong and Jiyun!

• 2024/10/21 - Our group's paper "PABLO: A Variation-Robust PIM Architecture for Bulk Bitwise Logical Operations in DRAM" has been accepted to IEEE Transactions on Emerging Topics in Computing.

• 2024/10/17 - Our group's paper "A 33.06 Gb/s Reconfigurable Galois Field oFEC Decoder for Optical Inter-Satellite Communication" has been accepted to IEEE Solid-State Circuits Letters.

• 2024/05/19 - Our group's paper "ParaBase: A Configurable Parallel Baseband Processor for Ultra-High-Speed Inter-Satellite Optical Communications" has been accepted to ISLPED'24. Congratulations!

• 2024/03/11 - Yeonsik and Gyuwan have joined our group as undergraduate researchers. Welcome!

• 2024/02/21 - Sungjun and Minje have joined our group as graduate research fellows. Welcome!

• 2024/02/14 - Our group's paper "MERSIT: A Hardware-Efficient 8-bit Data Format with Enhanced Post-Training Quantization DNN Accuracy" has been accepted to DAC'24. Congratulations!

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