Week 13:
- All Labs completed
- Finishing touches on Final Paper
- Brainstorming ties between D6 Project, DSD Project and Senior Design Project
Week 12:
- Finished Labs 4 & 5
- Finished Final Project Abstract and Goals
- Full steam ahead on Final Paper
Week 11:
- Finalized DSD Project: Understanding how FPGA's optimize High Frequency Trading Systems
- Continuing to work on Labs and make sure to update page in a timely fashion
Week 10:
Week 9:
- Contemplating Final Project
- Perhaps will work with QuEST Lab on their FPGA team projects
Week 8:
- First Online Lecture
- Started looking at Chapter 12, Looping Constructs
- for and while loops, next/exit commands
- Starting to work on labs without the physical board.
Week 7:
- No Class, Professor traveling
- COVID class manipulations
Week 5:
- Chapter 9: Structural Modeling in VHDL
- data-flow, behavioral & structural
Week 4:
- Worked on Lab 1 in Class
- Assembled the Nexys A7 Board and completed the Seven Digit Hex Counter
- Started looking at the code for the Hex Counter
Week 3:
- Navigated Vivado software
- Continued Chapters in textbook 4-6
Week 2:
- VHDL coding structure, differences from previous programming experiences. Downloaded Vivado. Covered Chapters 1-3 in the Free Range Textbook.
Week 1:
- Introduced to the idea of VHDL and Digital Circuit Simulations. Understood applications and use cases, advent of the technology and future of the industry