Labs

IMG_3705 2.MOV

Lab 1 : Seven Segment Hex Counter

In Lab 1 we, for the first time, synchronized the FPGA board to the Vivado VHDL software. The objective of the lab was to implement the VHDL code to have the FPGA board count in Hex by the means of manipulating the switches

Lab 2 : Four Digit Hex Counter

Unable to get the program to boot from the board because the "Add configuration memory device" was greyed out.

After troubleshooting, we were unable to get the program to boot from the board. Joined forces with another team who had a similar problem with adding the configuration memory device, but attempts were still unsuccessful
- We hypothesized that the issue was some sort of miscommunication or unconnected communication line between the local machine and the FPGA board.
The picture to the left shows the hex counter counting up

Lab 3 : Bouncing Ball

Followed GitHub directions to set up Bouncing Ball
Some error is occurring when x movement is trying to be altered, hoping to figure it out.

Lab 4 : Hex Calculator

Loaded hexcalc.xdc, hexcalc.vhd, leddec16.vhd and keypad.vhd into Vivado
Ran synthesis and implementation, generated bitstream
Unable to test on board so most I could do was dissect the code and modify things to better enhance my understanding

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY leddec16 IS

PORT (

dig : IN STD_LOGIC_VECTOR (1 DOWNTO 0); -- which digit to currently display

data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); -- 16-bit (4-digit) data

anode : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); -- which anode to turn on

seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); -- segment code for current digit

END leddec16;

ARCHITECTURE Behavioral OF leddec16 IS

SIGNAL data4 : STD_LOGIC_VECTOR (3 DOWNTO 0); -- binary value of current digit

BEGIN

-- Select digit data to be displayed in this mpx period

data4 <= data(3 DOWNTO 0) WHEN dig = "00" ELSE --digit 0

data(7 DOWNTO 4) WHEN dig = "01" ELSE --digit 1

data(11 DOWNTO 8) WHEN dig = "10" ELSE --digit 2

data(15 DOWNTO 12); --digit 3

-- Turn on segments corresponding to 4-bit data word

seg <= "0000001" WHEN data4 = "0000" ELSE --0

"1001111" WHEN data4 = "0001" ELSE --1

"0010010" WHEN data4 = "0010" ELSE --2

"0000110" WHEN data4 = "0011" ELSE --3

"1001100" WHEN data4 = "0100" ELSE --4

"0100100" WHEN data4 = "0101" ELSE --5

"0100000" WHEN data4 = "0110" ELSE --6

"0001111" WHEN data4 = "0111" ELSE --7

"0000000" WHEN data4 = "1000" ELSE --8

"0000100" WHEN data4 = "1001" ELSE --9

"0001000" WHEN data4 = "1010" ELSE --A

"1100000" WHEN data4 = "1011" ELSE --B

"0110001" WHEN data4 = "1100" ELSE --C

"1000010" WHEN data4 = "1101" ELSE --D

"0110000" WHEN data4 = "1110" ELSE --E

"0111000" WHEN data4 = "1111" ELSE --F

"1111111";

-- Turn on anode of 7-segment display addressed by 2-bit digit selector dig

anode <= "1110" WHEN dig = "00" ELSE -- digit 0

"1101" WHEN dig = "01" ELSE -- digit 1

"1011" WHEN dig = "10" ELSE -- digit 2

"0111" WHEN dig = "11" ELSE -- digit 3

"1111";

END Behavioral;

Lab 5 : DAC Siren

The objective of this lab was to create a Siren using DAC and Pmods.
Created and ran synthesis/implementation dac_if.vhd, siren.vhd, siren.xdc, tone.vhd, wail.vhd, and siren.xdc
ENTITY siren IS

PORT (

clk_50MHz : IN STD_LOGIC; -- system clock (50 MHz)

dac_MCLK : OUT STD_LOGIC; -- outputs to PMODI2L DAC

dac_LRCK : OUT STD_LOGIC;

dac_SCLK : OUT STD_LOGIC;

dac_SDIN : OUT STD_LOGIC

);

END siren;

ARCHITECTURE Behavioral OF siren IS

CONSTANT lo_tone : UNSIGNED (13 DOWNTO 0) := to_unsigned (344, 14); -- lower limit of siren = 256 Hz

CONSTANT hi_tone : UNSIGNED (13 DOWNTO 0) := to_unsigned (687, 14); -- upper limit of siren = 512 Hz

CONSTANT wail_speed : UNSIGNED (7 DOWNTO 0) := to_unsigned (8, 8); -- sets wailing speed

COMPONENT dac_if IS

PORT (

SCLK : IN STD_LOGIC;

L_start : IN STD_LOGIC;

R_start : IN STD_LOGIC;

L_data : IN signed (15 DOWNTO 0);

R_data : IN signed (15 DOWNTO 0);

SDATA : OUT STD_LOGIC

);

END COMPONENT;

COMPONENT wail IS

PORT (

lo_pitch : IN UNSIGNED (13 DOWNTO 0);

hi_pitch : IN UNSIGNED (13 DOWNTO 0);

wspeed : IN UNSIGNED (7 DOWNTO 0);

wclk : IN STD_LOGIC;

audio_clk : IN STD_LOGIC;

audio_data : OUT SIGNED (15 DOWNTO 0)

Lab 6 : Pong

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