- 2025-
51. [VLSI 2025] S. Kim, H. Kwon, J. lee, Y. Moon, H. Lee, J. Ryu, Z. Kalzhan, Sangyeob Kim, W. Jo, and Hoi-jun yoo
"Nuvpu: A 4.8∼9.6∼mJ / Frame Progressive NTT-Based Unified Video Processor for Stable Video Streaming and Processing with Neural Video Codec," 2025 IEEE Symposium on VLSI Technology and Circuits
50. [HOTCHIPS 2025] S. Kim, J. Oh, J. So, Y. Choi, Sangyeob Kim, D. Im, G. Park, Hoi-Jun Yoo
"EdgeDiff: Multi-modal Few-step Diffusion Model Accelerator with Mixed-Precision and Reordered Group-Quantization for On-device Generative AI Motivation" 2025 IEEE Hot Chips 37 Symposium
49. [HOTCHIPS 2025] W. Jo, S. Hong, J. Choi, B. Kwon, H. Sang, D. Im, Sangyeob Kim, S. Kim, C. Jeong, Y. Moon, Hoi-Jun Yo
"BROCA: A Low-power and Low-latency Conversational Agent RISC-V System-on-Chip for Voice-interactive Mobile Devices," 2025 IEEE Hot Chips 37 Symposium
48. [HOTCHIPS 2025] Sangyeob Kim, J. Lee, B. Kim, and Hoi-Jun Yoo
"A 4.69mW LLM Processor with Binary/Ternary Weights for Billion-Parameter Llama Model," 2025 IEEE Hot Chips 37 Symposium
47. [ISCAS 2025] N.Lee, Sangyeob Kim, S.Hong, J.Choi, and Hoi-Jun Yoo
"A 65.1 TOPS/W Digital CIM Processor for Ultra-Low-Bit Transformers with Multiplexer-Based Adder and Scaling Factor-Based Reordering," 2025 IEEE International Symposium on Circuits and Systems
46. [ISSCC 2025] Sangyeob Kim, J.Lee, and Hoi-Jun Yoo
"Slim-Llama: A 4.69mW Large-Language-Model Processor with Binary/Ternary Weights for Billion-Parameter Llama Model," 2025 IEEE International Solid-State Circuits Conference
45. [ISSCC 2025] W. Jo, S. Hong, J. Choi, B. Kwon, H. Sang, D. Im, Sangyeob Kim, S. Kim, and Hoi-Jun Yoo
"BROCA: A 52.4-559.2mW Mobile Social Agent System-on-Chip with Adaptive-Bit-Truncate Unit and Acoustic-Cluster Bit-Grouping ," 2025 IEEE International Solid-State Circuits Conference
44. [ISSCC 2025] S. Kim, J. Oh, J. So, Y. Choi, Sangyeob Kim, D. Im, G. Park, and Hoi-Jun Yoo
"EdgeDiff: 418.4mJ/inference Multi-modal Few-step Diffusion Model Accelerator with Mixed-Precision and Reordered Group-Quantization," 2025 IEEE International Solid-State Circuits Conference
- 2024-
43. [HOTCHIPS 2024] Sangyeob Kim, S.Kim, W.Jo, S.Kim, S.Hong, N.Lee, and Hoi-Jun Yoo
"A Low-power Large-Language-Model Processor with Big-Little Network and Implicit-Weight-Generation for On-device AI," 2024 IEEE Hot Chips 36 Symposium
42. [HOTCHIPS 2024] J.Ryu, H.Kwon, W.Park, Z.Li, B.Kwon, D.Han, D.Im, Sangyeob Kim, H.Joo, M.Kim and Hoi-Jun Yoo
"NeuGPU: A Neural Graphics Processing Unit for Instant Modeling and Real-Time Rendering on Mobile AR/VR Devices," 2024 IEEE Hot Chips 36 Symposium
41. [HOTCHIPS 2024] G.Park, S.Song, H.Sang, D.Im, D.Han, Sangyeob Kim, H.Lee, and Hoi-Jun Yoo
"Space-Mate: A 303.5mW Real-Time NeRF SLAM Processor with Sparse Mixture-of-Experts-based Acceleration," 2024 IEEE Hot Chips 36 Symposium
40. [VLSI 2024] S.Kim, S.Song, W.Park, J.Ryu, Sangyeob Kim, G.Park, S.Kim, and Hoi-Jun Yoo
"NeRF-Navi: A 93.6-202.9μJ/task Switchable Approximate-Accurate NeRF Path Planning Processor with Dual Attention Engine and Outlier Bit-Offloading Core," 2024 IEEE Symposium on VLSI Technology and Circuits
39. [VLSI 2024] S.Hong, W.Jo, S.Kim, Sangyeob Kim, K.Sohn, and Hoi-Jun Yoo
"Dyamond: A 1T1C DRAM In-memory Computing Accelerator with Compact MAC-SIMD and Adaptive Column Addition Dataflow," 2024 IEEE Symposium on VLSI Technology and Circuits
38. [COOLCHIPS 2024] S.Kim, Z.Li, S.Um, W.Jo, S.Ha, Sangyeob Kim, and Hoi-Jun Yoo
"NoPIM: Functional Network-on-Chip Architecture for Scalable High-Density Processing-in-Memory-based Accelerator," 2024 IEEE Symposium in Low-Power and High-Speed Chips
37. [COOLCHIPS 2024] G.Park, S.Song, H.Sang, D.Im, D.Han, Sangyeob Kim, H.Lee, and Hoi-Jun Yoo
"A Low-power and Real-time Neural-Rendering Dense SLAM Processor with 3-Level Hierarchical Sparsity Exploitation," 2024 IEEE Symposium in Low-Power and High-Speed Chips
36. [COOLCHIPS 2024] J.Ryu, H.Kwon, W.Park, Z.Li, B.Kwon, D.Han, Sangyeob Kim, H. Joo, and Hoi-Jun Yoo
"A Low-Power Neural Graphics System for Instant 3D Modeling and Real-Time Rendering on Mobile AR/VR Devices," 2024 IEEE Symposium in Low-Power and High-Speed Chips
35. [AICAS 2024] S.Hong, Sangyeob Kim, S.Kim, and Hoi-Jun Yoo
"DualNet: Efficient Integration of Artificial Neural Network and Spiking Neural Network with Equivalent Conversion," 2024 IEEE International Conference on Artificial Intelligence Circuits and Systems
34. [ISSCC 2024] Sangyeob Kim, S.Kim, W.Jo, S.kim, S.Hong, and Hoi-Jun Yoo
"C-Transformer: A 2.6-18.1μJ/Token Homogeneous DNN-Transformer/Spiking-Transformer Processor with Big-Little Network and Implicit Weight Generation for Large Language Models," 2024 IEEE International Solid-State Circuits Conference
33. [ISSCC 2024] G.Park, S.Song, H.Sang, D.Im, D.Han, Sangyeob Kim, H.Lee, and Hoi-Jun Yoo
"Space-Mate: A 303.5mW Real-Time Sparse Mixture-of-Experts-Based NeRF-SLAM Processor for Mobile Spatial Computing," 2024 IEEE International Solid-State Circuits Conference
32. [ISSCC 2024] J.Ryu, H.Kwon, W.Park, Z.Li, B.Kwon, D.Han, D.Im, Sangyeob Kim, H.Joo, and Hoi-Jun Yoo
"NeuGPU: A 18.5 mJ/Iter Neural-Graphics Processing Unit for Instant-Modeling and Real-Time Rendering with Segmented-Hashing Architecture," 2024 IEEE International Solid-State Circuits Conference
- 2023-
31. [ASSCC 2023] J.Choi, Sangyeob Kim, W.Park, W.Jo, and Hoi-Jun Yoo
"A Resource-Efficient Super-Resolution FPGA Processor with Heterogeneous CNN and SNN Core Architecture," 2023 IEEE Asian Conference on Solid-State Circuits
30. [ASSCC 2023] S.Um, S.Kim, S.Hong, Sangyeob Kim, and Hoi-Jun Yoo
"LOG-CIM: A 116.4 TOPS/W Digital Computing-In-Memory Processor Supporting a Wide Range of Logarithmic Quantization with Zero-Aware 6T Dual-WL Cell," 2023 IEEE Asian Conference on Solid-State Circuits
29. [VLSI 2023] W.Jo, S.Kim, J.Lee, D.Han, Sangyeob Kim, S.Choi, and Hoi-Jun Yoo
"NeRPIM: A 4.2 mJ/frame Neural Rendering Processing-in-memory Processor with Space Encoding Block-wise Mapping for Mobile Devices," 2023 IEEE Symposium on VLSI Technology and Circuits
28. [VLSI 2023] S.Song, D.Han, S.Kim, Sangyeob Kim, G.Park, and Hoi-Jun Yoo
"GPPU: A 330.4-µJ/task Neural Path Planning Processor with Hybrid GNN Acceleration for Autonomous 3D Navigation," 2023 IEEE Symposium on VLSI Technology and Circuits
27. [VLSI 2023] W.Xie, H.Sang, B.Kwon, D.Im, S.Kim, Sangyeob Kim, and Hoi-Jun Yoo
"A 709.3 TOPS/W Event-Driven Smart Vision SoC with High-Linearity and Reconfigurable MRAM PIM," 2023 IEEE Symposium on VLSI Technology and Circuits
26. [COOLCHIPS 2023] Sangyeob Kim, S.Kim, S.Hong, S.Kim, D.Han, J.Choi and Hoi-Jun Yoo
"COOL-NPU: Complementary Online Learning Neural Processing Unit with CNN-SNN Heterogeneous Core and Event-driven Backpropagation," 2023 IEEE Symposium in Low-Power and High-Speed Chips
25. [COOLCHIPS 2023] D.Han, J.Ryu, Sangyeob Kim, S.Kim, J.Park, and Hoi-Jun Yoo
"A Low-power Neural 3D Rendering Processor with Bio-inspired Visual Perception Core and Hybrid DNN Acceleration," 2023 IEEE Symposium in Low-Power and High-Speed Chips
24. [ISCAS 2023] S.Hong, S.Um, S.Kim, Sangyeob Kim, W.Jo, and Hoi-Jun Yoo
"A 332 TOPS/W Input/Weight-Parallel Computing-in-Memory Processor with Voltage-Capacitance-Ratio Cell and Time-Based ADC," 2023 IEEE International Symposium on Circuits and Systems
23. [ISCAS 2023] W.Park, J.Ryu, S.Kim, S.Um, W.Jo, Sangyeob Kim, and Hoi-Jun Yoo,
"A 5.99 TFLOPS/W Heterogeneous CIM-NPU Architecture for an Energy Efficient Floating-Point DNN Acceleration," 2023 IEEE International Symposium on Circuits and Systems
22. [ISCAS 2023] S.Kim, S.Kim, S.Um, S.Kim, Z.Li, Sangyeob Kim, W. Jo, and Hoi-Jun Yoo,
"A Reconfigurable 1T1C eDRAM-based Spiking Neural Network Computing-In-Memory Processor for High System-Level Efficiency," 2023 IEEE International Symposium on Circuits and Systems
21. [ISSCC 2023] Sangyeob Kim, S.Kim, S.Hong, S.Kim, D.Han, and Hoi-Jun Yoo
"C-DNN: A 24.5-85.8TOPS/W Complementary-Deep-Neural-Network Processor with Heterogeneous CNN/SNN Core Architecture and Forward-Gradient-Based Sparsity Generation," 2023 IEEE International Solid-State Circuits Conference
20. [ISSCC 2023] D.Han, J.Ryu, Sangyeob Kim, S.Kim, and Hoi-Jun Yoo
"MetaVRain: A 133mW Real-time Hyper-realistic-3D-NeRF Processor with 1D-2D Hybrid-Neural-Engines for Metaverse on Mobile Devices," 2023 IEEE International Solid-State Circuits Conference
19. [ISSCC 2023] S.Kim, Z.Li, S.Um, W.Jo, S.Ha, J.Lee, Sangyeob Kim, D.Han, and Hoi-Jun Yoo
"DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource Switching," 2023 IEEE International Solid-State Circuits Conference
- 2022-
18. [ASSCC 2022] Sangyeob Kim, S. Kim, S. Um, S. Kim, J. Lee and Hoi-Jun Yoo,
"SNPU: Always-on 63.2uW Face Recognition Spike Domain Convolutional Neural Network Processor with Spike Train Decomposition and Shift-and-Accumulation Unit," 2022 IEEE Asian Solid-State Circuits Conference
17. [HOTCHIPS 2022] Sangyeob Kim, S. Kim, S. Um, S. Kim, K. Kim and Hoi-Jun Yoo,
"Neuro-CIM: A 310.4 TOPS/W Neuromorphic Computing-in-Memory Processor with Low WL/BL activity and Digital-Analog Mixed-mode Neuron Firing," 2022 IEEE Hot Chips 34 Symposium
16. [VLSI 2022] Sangyeob Kim, S.Kim, S.Um, S.Kim, K.Kim, and Hoi-Jun Yoo
"Neuro-CIM: A 310.4 TOPS/W Neuromorphic Computing-in-Memory Processor with Low WL/BL activity and Digital-Analog Mixed-mode Neuron Firing," 2022 IEEE Symposium on VLSI Technology and Circuits
- 2021-
15. [HOTCHIPS 2021] J.Lee, Sangyeob Kim, J. Kim, S. Kim, W.Jo, D. Han, and Hoi-Jun Yoo,
"OmniDRL: An Energy-Efficient Mobile Deep Reinforcement Learning Accelerators with Dual-mode Weight Compression and Direct Processing of Compressed Data," 2021 IEEE Hot Chips 33 Symposium
14. [HOTCHIPS 2021] J.Lee, J.Kim, W.Jo, Sangyeob Kim, S. Kim, D. Han, J. Lee, and Hoi-Jun Yoo
"An Energy-efficient Floating-Point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory," 2021 IEEE Hot Chips 33 Symposium
13. [AICAS 2021] J.Lee, C.Kim, D.Han, Sangyeob Kim, S.Kim, and Hoi-Jun Yoo
"Energy-Efficient Deep Reinforcement Learning Accelerator Designs for Mobile Autonomous Systems," 2021 IEEE International Conference on Artificial Intelligence Circuits and Systems
12. [VLSI 2021] J.Lee, Sangyeob Kim, S.Kim, W.Jo, D.Han, J.Lee, and Hoi-Jun Yoo
"OmniDRL: A 29.3 TFLOPS/W Deep Reinforcement Learning Processor with Dual-mode Weight Compression and On-chip Sparse Weight Transposer," 2021 IEEE Symposium on VLSI Technology and Circuits
11. [VLSI 2021] J.Lee, J.Kim, W.Jo, Sangyeob Kim, S.Kim, J.Lee, and Hoi-Jun Yoo
"A 13.7 TFLOPS/W Floating-point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory," 2021 IEEE Symposium on VLSI Technology and Circuits
10. [ISCAS 2021] S.Um, Sangyeob Kim, S.Kim, and Hoi-Jun Yoo,
"A 43.1TOPS/W Energy-Efficient Absolute-Difference-Accumulation Operation Computing-In-Memory with Computation Reuse," 2021 IEEE International Symposium on Circuits and Systems
9. [ISCAS 2021] S.Kim, S.Kim, Sangyeob Kim, D.Han, and Hoi-Jun Yoo,
"A 64.1mW Accurate Real-time Visual Object Tracking Processor with Spatial Early Stopping on Siamese Network," 2021 IEEE International Symposium on Circuits and Systems
- 2020-
8. [ASSCC 2020] S.Kim, S.Kang, D.Han, Sangyeob Kim, S.Kim, and Hoi-Jun Yoo
"An Energy-Efficient GAN Accelerator with On-chip Training for Domain Specific Optimization," 2020 IEEE Asian Conference on Solid-State Circuits
7. [HOTCHIPS 2020] S.Kang, D.Han, J.Lee, D.Im, Sangyeob Kim, S. Kim, J.Ryu, and Hoi-Jun Yoo, "GANPU: A Versatile Many-Core Processor for Training GAN on Mobile Devices with Speculative Dual-Sparsity Exploitation," 2020 IEEE Hot Chips 32 Symposium
6. [ISCAS 2020] S.Kim, Sangyeob Kim, J.Lee, and Hoi-Jun Yoo,
"A 54.7 fps 3D Point Cloud Semantic Segmentation Processor with Sparse Grouping Based Dilated Graph Convolutional Network for Mobile Devices," 2020 IEEE International Symposium on Circuits and Systems
5. [VLSI 2020] Sangyeob Kim, J.Lee, S.Kang, J.Lee, and Hoi-Jun Yoo
"A 146.52 TOPS/W Deep-Neural-Network Learning Processor with Stochastic Coarse-Fine Pruning and Adaptive Input/Output/Weight Skipping," 2020 IEEE Symposium on VLSI Technology and Circuits
4. [ISSCC 2020] S.Kang, D.Han, J.Lee, D.Im, Sangyeob Kim, and Hoi-Jun Yoo
"GANPU: A 135TFLOPS/W Multi-DNN Training Processor for GANs with Speculative Dual-Sparsity Exploitation," 2020 IEEE International Solid-State Circuits Conference
- 2019-
3. [ISCAS 2019] Sangyeob Kim, J. Lee, S. Kang, J. Lee and Hoi-Jun Yoo
"A 15.2 TOPS/W CNN Accelerator with Similar Feature Skipping for Face Recognition in Mobile Devices," 2019 IEEE International Symposium on Circuits and Systems
- 2018-
2. [HOTCHIPS 2018] J.Lee, C.Kim, S.Kang, D.Shin, Sangyeob Kim, and Hoi-Jun Yoo,
"An Energy-Efficient Unified Deep Neural Network Accelerator with Fully-Variable Weight Precision for Mobile Deep Learning Applications," 2018 IEEE Hot Chips 30 Symposium
1. [ISSCC 2018] J.Lee, C.Kim, S.Kang, D.Shin, Sangyeob Kim, and Hoi-Jun Yoo
"UNPU: A 50.6TOPS/W Energy-Efficient Unified Deep Neural-Network Accelerator with 1-to-16b Fully Variable Bit Precision," 2018 IEEE International Solid-State Circuits Conference