CV

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Education:

Indian Institute of Technology Delhi (2019 – Present)

Ph.D., Electrical Engineering

• Coursework CGPA: 9.75/10

• Supervisors: Prof. Soumya Nag, Prof. Anandarup Das

National Institute of Technology Srinagar (2015 – 2019)

B.Tech., Electrical Engineering

• CGPA: 8.8/10 (3rd Rank)

Research Experience:

Non-Isolated Three Phase Unfolding Based Electric Vehicle Powertrain

Doctoral Research at IIT Delhi

• Investigated quasi single-stage three phase unfolding based dc-ac conversion as an alternative to conventional two-stage electric vehicle powertrain.

• While most existing three-phase unfolding systems use two full power isolated converters in dc-dc stage, the proposed system is implemented using a full power non-inverting buck-boost (NIBB) and a partial power processing (<60% of full power) balancer circuit.

• Detailed analytical loss modelling demonstrated higher efficiency compared to conventional boost-cascaded VSI powertrain, owing to fewer high frequency switching half-bridges and the fundamental frequency switching inverter stage in the proposed system.

• The highly sinusoidal output (voltage THD<2%) eliminates high dV/dt common-mode voltages, reducing bearing currents, and motor terminal overvoltages due to wave reflections.

Input-Parallel Output-Series Connected Non-Isolated High Power DC-DC Converters

Doctoral Research at IIT Delhi

• Input-parallel output-series (IPOS) connections of basic modules are beneficial for high voltage dc applications (like two-stage powertrains) but require at least one isolated module.

• Proposed novel buck-boost dc-dc converters based on IPOS connection of regular and floating versions of basic non-isolated modules. Proposed converters include a symmetric connection of two NIBB modules, and an asymmetric connection of an NIBB module and a boost module.

• The converters feature reduced semiconductor ratings (e.g., 750/900 V devices instead of 1200 V) due to IPOS connection leading to higher switch utilization compared to other buck-boost converters, including the standalone NIBB converter. Module interleaving together with lower maximum voltage and current stress results in reduced filter energy ratings (45% reduction compared to NIBB).

• Efficiency is enhanced by disabling modules for low output voltage requirement and transitioning to multi-module operation for high voltage requirement only.

Linear Quadratic Regulator Based Control of Inverted Pendulum Problem

Undergraduate Project at NIT Srinagar

• Modelled and simulated classical inverted pendulum control problem having unstable and non-linear dynamics.

• Implemented a hybrid control scheme with energy swing-up control and a balancing linear quadratic regulator (LQR) control. Successfully deployed on a rotary inverted pendulum trainer by National Instruments using LabVIEW software.

Hardware Development:

25 kW SiC Based Interleaved Asymmetric IPOS Doctoral Research at IIT Delhi

Doctoral Research at IIT Delhi

• Developed a three-phase interleaved converter with each phase being an IPOS connection of NIBB and boost modules rated for 8 kW.

• Utilized 650 V and 750 V SiC devices for output voltage up to 800 V from 350 V input with 100 kHz switching. Power density of 3.5 kW/L with forced air cooling.

• Pass-through operation up to 550 V output, with measured peak efficiency above 99%. Above 98% efficiency from 10% to 100% load with phase shedding control.

5 kW SiC Based Three Phase Unfolding Motor Drive Prototype

Doctoral Research at IIT Delhi

• Implemented a non-isolated three phase unfolding powertrain using a T-type unfolder and NIBB and balancer circuit in the dc-dc stage, rated for 300-400 V input and 415 Vrms output.

• DC-DC stage inductances designed to achieve quasi-square wave ZVS at a fixed switching frequency of 100 kHz with isolated gate drivers.

• Applied model reference adaptive system (MRAS) based speed sensorless vector control on a 5 hp, 1500 rpm induction machine using TI TMS320F28379D DSP. Tested with class 3 Worldwide Harmonised Light Vehicle Test Procedure (WLPT) drive cycle with an EV emulated load.

• Peak efficiency of 98.4% at 3.24 kW with efficiencies greater than 97% for most of speed-torque region. Highly sinusoidal outputs with voltage THD of 1.7 % at 415 V.

5 kW Symmetric IPOS Buck-Boost DC-DC Converter Prototype

Doctoral Research at IIT Delhi

• Symmetric IPOS connection of two NIBB modules with all SiC devices & sendust core inductors.

• Tested with ECE 15 drive cycle up to 800 V output, with peak efficiency above 98% for output voltages of 250 V, 500 V, and 800 V.

DSP/FPGA Control Interface and Differential Voltage/Current Sensing Boards

Doctoral Research at IIT Delhi

• Developed a control interface board to improve functionality and increase PWM outputs of TI TMS320F28379D DSP using an Altera Cyclone II FPGA.

• Developed voltage and current sensing boards with multiple feedback filtering and differential outputs for better noise immunity.

500 W Three Phase Interleaved Buck Converter and Grid-Connected Microinverter

Postgraduate Course Projects at IIT Delhi

• Built a 500 W Si based interleaved buck converter with phase shedding control.

• Designed and tested a 500 W single-phase grid-connected microinverter.

Technical Skills:

• MATLAB, Simulink, Spice based system and converter simulations.

• Converter modelling and analytical loss analysis using datasheet parameters.

• Digital control using DSPs (TI C2000) and FPGAs (Altera Cyclone).

• Magnetics and thermal design using Ansys.

• PCB design using KiCad, Altium.