Description

Problem Statement : 8 bits 3 address modes with immediate addressing. 

Description: 

This circuit showcases an 8-bit processor specifically designed to handle simple computational tasks in immediate addressing mode. Its streamlined architecture and 3-bit addressing scheme make it a lightweight and efficient model, ideal for educational demonstrations or small-scale projects.

Key Features of the Processor

1. 8-bit Architecture

• Data Size: The processor handles 8-bit data, allowing operations and instructions to work on 8-bit operands.

• 
  

2. 3-bit Addressing Scheme

• Memory Capacity:

  • Memory addresses are represented using 3 bits, enabling access to 23=82^3 = 823=8 distinct memory locations.

  • While compact, this memory space limits the size of programs and data the processor can handle.

3. Immediate Addressing Mode

• Embedded Operands: In this mode, the required data is directly included in the instruction itself, bypassing the need to fetch it from memory or registers.

• Advantage: This results in faster execution since it reduces the number of memory access steps.

4. Instruction Processing Cycle

• Stages of Execution:

  1. Fetch:

     • The Program Counter (PC) provides the address of the upcoming instruction.

     • The instruction is retrieved from code memory and stored in the Instruction Register (IR).

  2. Decode:

     • The Control Unit (CU) interprets the fetched instruction, determining the operation and its operands.

  3. Execute:

     • The Arithmetic Logic Unit (ALU) carries out the operation, or data is moved between memory and registers.

5. Fundamental Components

• Registers: Small storage units used for temporarily holding data and results during processing.

• Arithmetic Logic Unit (ALU): Performs mathematical computations (like addition) and logical evaluations (like AND, OR).

• Control Unit (CU):

  • Manages the flow of data and operations across the processor.

  • Deciphers instructions and coordinates the activities of other components.

• Program Counter (PC):

  • Points to the memory address of the next instruction to be executed.

  • Advances automatically unless a jump or branch alters the sequence.

• Instruction Register (IR): Temporarily holds the active instruction while it is being processed.

6. Code Memory

• Program Storage: Houses the program’s instructions in binary format.

• Capacity Limitations:

  • The 3-bit address scheme restricts the memory to 8 locations.

  • Suitable for simple programs, reflecting the educational purpose of the processor.

7. Synchronized Operation

• Relies on a clock signal to coordinate operations across all modules.

• Ensures that instructions are executed in a structured and orderly manner.

8. Status Indicators (Flags)

• Zero Flag (RZ):

  • Set when the result of an ALU operation is zero.

  • Useful for decision-making in conditional branches or loops.