Learnings from the Activity
Understanding Processor Design Basics
Learned how the instruction lifecycle (fetch, decode, execute, and write-back) is implemented in a processor.
Gained insight into how a 3-address instruction format works, where three operands are explicitly specified.
Instruction Set Design
Created an instruction set supporting arithmetic and logical operations.
Incorporated immediate addressing, where one of the operands is embedded directly in the instruction.
Register and Memory Architecture
Designed a register file to hold temporary data during execution.
Understood how to handle data flow between registers and memory.
Control Unit Implementation
Developed a control unit capable of decoding instructions and generating control signals for the ALU, memory, and registers.
Explored how to handle different instruction formats using micro-operations.
ALU Integration
Integrated an 8-bit ALU to perform arithmetic and logical operations as part of the execution cycle.
Data Path Design
Designed the data path for an 8-bit processor, including buses for data movement, multiplexers, and selectors.
Simulation and Debugging
Simulated the processor using tools like Logisim, debugging issues with incorrect data flow, or logical errors in instruction execution.
Challenges Faced
Instruction Format Complexity
Designing a 3-address format while maintaining the instruction width at 8 bits was challenging due to limited space for opcode and operands.
Control Signal Design
Generating the right control signals for each instruction type was tricky, especially for immediate addressing.
ALU Operations
Ensuring the ALU performed all required operations (like addition, subtraction, and logical operations) without affecting the processor's performance.
Memory Access
Handling immediate values alongside memory/register operands was confusing initially, especially when juggling different addressing modes.
Debugging in Simulation
Debugging issues in Logisim was time-consuming, especially when control signals didn’t behave as expected or registers didn’t update correctly.