Projects
Projects
Embedded Files
November 2023
November 2023
Ring Learning With Errors(R-LWE) Decryption Module
Ring Learning With Errors(R-LWE) Decryption Module
Implemented the decyrption module comprising of a binary multiplier and thresholder for a R-LWE cryptosystem in verilog.
EC592 Course Project under Dr. Aydin Aysu
November 2023
November 2023
Dynamic Instruction Scheduling Timing Simulator
Dynamic Instruction Scheduling Timing Simulator
Implemented a C++ simulator to model the timing of a hypothetical RISC-V-based processor with a variable latency execution unit, forwarding and reorder buffer for dynamic execution of instructions.
Analyzed the impact of parameter changes like the size of issue queue, superscalar width and reorder buffer on the IPC of a processor
EC563 Course Project under Dr. Eric Rotenberg.
September –
September –
October 2023
October 2023
AES Implementation and DPA
AES Implementation and DPA
Implemented S-Box based AES encryption and decryption modules in Python.
Performed a DPA attack for key extraction using a provided power trace run from a modified AES implementation on a Sakura FPGA.
EC592 Course Project under Dr. Aydin Aysu.
October- November 2023
October- November 2023
Branch Prediction Simulator
Branch Prediction Simulator
Modelled a gshare, bimodal and hybrid branch predictor in C++.
Analyzed the impact of parameter changes on the misprediction rate.
EC563 Course Project under Dr. Eric Rotenberg
September- October 2023
September- October 2023
Cache Simulator
Cache Simulator
Implemented a 2-level cache model (using LRU and WBWA) with a prefetch buffer in C++.
Analyzed the impact of cache sizes and various configurations on miss rate.
EC563 Course Project under Dr. Eric Rotenberg
January 2023
January 2023
– April 2023
– April 2023
Major_Project_Final_Report.pdfA Configurable Framework for CNN Implementations on Hardware
A Configurable Framework for CNN Implementations on Hardware
Designed and implemented re-configurable memory architectures on FPGA/s for feeding image inputs into a convolutional kernel with optimized LUT and BRAM utilization as well as latency, while taking advantage of the redundancies found in typical CNN implementations.
Tested out the latencies and generated a report comparing the designed architectures.
B.Tech Thesis/Major Project under Dr. Sumam David.
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