Projects
January 2022
– April 2022
VLSI_MP_191EC126_191EC145_compressed.pdfRISC-V based micro-controller using OpenLane
Synthesized a GDSII layout from verilog code of the open source RISC-V based microprocessor PICORV32a.
Re-synthesized new GDSII layout with various modules enabled and reported changes in timing slack, area as well as power consumption.
Identified a bug in OpenLane where timing violations are not reported in the final report despite intermediate worst slack being negative.
Tried out fast-routing techniques due to the large run-time and various output capacitance, and drive strengths to improve slack.
Identified longest path from worst slack reports and fixed timing violations.
Generated the final layout using Klayout.
Course Project under Dr. Ramesh Kini, NITK
January 2022
– April 2022
EC440_Report_191EC126_191EC145.pdfSimple RISC based Microprocessor using OpenLane
Modified the verilog code of the simple RISC microprocessor "beta" previously synthesized in Vivado to contain suitable IO pins for Yosys RTL simulation of Openlane.
Identified interactive mode commands from the TCL Script due to outdated OpenLane documentation.
Identified the cause of pin violations as antenna effect and reduced the antenna effect with diode insertion.
Synthesized successful GDSII design with a frequency of 250 MHz after fixing timing violations.
Course Project under Dr. Ramesh Kini, NITK