Projects & PUBLICATIONS
Design and development of fully programmable reconfigurable Mixed Analog AI Accelerator chip called ARYABHAT for Machine learning and Edge computing Aug 2019 - Dec 2023
This research focuses on building the first-of-its-kind technology scalable reconfigurable analog processor that can be fully scaled down to sub-nanometer process nodes. The processor is called ARYABHAT (Analog Reconfigurable TechnologY And Bias-Scalable Hardware For AI Tasks)
ARYABHAT-1 is a next-generation analog computing chipset designed to target Artificial-Intelligence (AI) and Machine Learning (ML) applications at the edge. Presently, such computations are achieved by application-specific digital accelerators which utilize spatial arrays of parallel processing elements to significantly improve performance and energy efficiency compared to general purpose platforms. For more details, please click on Project Link.
Design and prototyping of Neuromorphic Field Programmable Computational Array (NFPCA) for Machine Learning and Edge AI (Artificial Intelligence) Jan 2020 - Ongoing
This ongoing research focuses on prototyping a neurally inspired programmable computational array based on an approximate computing framework with tunable accuracy.
The system could be programmed to implement most machine learning algorithms with low energy and area footprints. Currently, the fabricated prototype is in the testing phase.
Automated design and synthesis of unconventional Analog AI Accelerator chip using standard Digital ASIC flow Mar 2022 - Ongoing
The goal of this project is to create a framework that can automatically synthesize a fully analog deep learning accelerator similar to its digital synthesis step for faster prototyping.
It combines novel concepts of analog-approximate computing, design optimization, and an Open Source process design kit to create a single multi-level algorithmic framework for deep learning analog accelerator design.
Design of Process, Bias and Temperature Scalable Analog Standard Cells for Machine Learning Mar 2021 - Jan 2022
The goal of this research was to create robust analog standard cells just like digital standard cells and utilize those to build high-performance analog compute systems.
Utilizing the Shape Based Analog Computing framework, we built and demonstrated analog cells that are invariant to transistor operating regimes, modular just like digital design, robust to non-idealities of devices, and simultaneously technology scalable.
Design of Shape-Based Analog Computing Framework for Machine Learning Mar 2021 - Dec 2021
The research aims at creating a novel analog computing framework that allows the user to create analog computational functions simply by identifying the desired shape.
The framework allows the user to create a robust transfer function with tunable accuracy and introduces the concept of design margin in analog computing, similar to noise margin in digital.
Development of code-based Rapid Analog Design framework using Gm/Id Design and Pre-computed Lookup Tables Aug 2021 - Ongoing
Designed and implemented code-analog circuits using Matlab lookup tables and trans-conductance efficiency as an approximation.
Designed code basic computational models such as Intrinsic gain stages, Common-Source amplifiers, Constant trans-conductance bias circuit, Cascode current mirror, Advanced cascode current mirror, Single-stage opamp, etc. using code-based analog design.
Design of Open-Source automated test framework using PyVISA, Python & TCP for analog chip testing Jun 2021 - Ongoing
This work deals with the creation of an in-house open-source framework for rapid analog testing.
We designed a one-stop automated solution for testing and reporting massively large analog machine learning chips.
The framework integrates different test equipment from different vendors such as Keithley, Rigol on a single platform Python, and is generic enough to run on any PC for automated testing and reporting.
Design & implementation of a novel hybrid computational system that utilizes inherent MOS device mismatch and multi-state memory for Machine Learning at the Edge Oct 2019 - Dec 2021
This research focused on designing and prototyping a novel hybrid neural network architecture in CMOS technology that utilizes inherent analog device mismatch ( a shortcoming in traditional CMOS) to offer efficient design in terms of area and power.
The architecture is generic enough to be used with novel multi-state memory devices such as memristor, 2D-Materials, and others.
Design & implementation of energy-efficient wake-up architecture for Edge computing Dec 2018 - Dec 2019
This work focused on designing an intelligent analog wake-up system that can be embedded directly onto low power, small area, and computationally efficient hardware devices.
This architecture utilizes our novel high-performance, ultra-low-power molybdenum disulfide (MoS2) based two-dimensional synaptic memtransistor as an analog memory and exploits random device mismatches to implement a population coding scheme.
Design of middleware for large scale spiking neuromorphic processors Mar 2019 - Oct 2019
This work focused on a middleware that can efficiently map standard machine learning algorithms onto spiking neuromorphic processors.
At the core of the proposed approach is margin-propagation (MP) computing that is naturally implemented by a network of integrate-and-fire (I&F) neurons. As a result, the middleware can exploit computational primitives inherent in routing and statistical combination of Poisson spikes to implement synaptic multiplication and somatic integration.
The resulting spike-based computation is not only faster than other time-based computing approaches, but the proposed middleware also obviates any redesign of existing neuromorphic hardware
Proposition and design of novel template SVM algorithm framework for memory constrained Edge applications Jan 2019 - Aug 2019
This work focused on designing a novel framework for support vector machines (SVMs) that does not restrict the SVM kernel to be positive-definite and allows the user to define memory constrains in terms of fixed template vectors.
This makes the framework scalable and enables its implementation for low-power, high-density, and memory-constrained embedded applications. We also showed the implementation using memtransistor cross-bar array and its robustness to device mismatch and randomness.
Design of high-frequency Memristor, Meminductor and Memcapacitor emulators Aug 2017 - Aug 2018
This work deals with the design, implementation, and prototyping of novel multi-state memories such as Memristor, Meminductors, and Memcapacitors in CMOS. OTA-based novel high-frequency emulators were designed, proposed, and tested.
Applications of those emulators as Amplitude Modulator and Chaotic oscillators were also shown. The performance of all the proposed circuits has been verified with Cadence Virtuoso, and prototypes were tested on AD844.
Design of Three-Tier Test Automation architecture for IBM Rational Functional Tester Jan 2016 - Aug 2016
This project dealt with the design of a framework specifically for IBM Rational Functional Tester tool.
The script integrated with tools allows the end-user to perform better automated testing. Here, a flexible and customized three-tier architecture was implemented in JAVA, where app-objects, tasks, and test scripts are at its core.
Open Source framework design for test automation using Selenium, Eclipse, Maven and TestNG Jan 2015 - Oct 2015
This project deals with the development of a one-click open-source test automation framework from scratch for multiple clients.
The framework and the related scripts were designed using Java from scratch and utilized Selenium, Maven, Eclipse, and TestNG.
Design of Semi Intelligent Multi-functional Bot Jul 2013 - May 2014
This project was to design a Semi Intelligent multi-functional robot that had properties such as obstacle avoidance, light following, intruder detecting, pathfinding, and temperature sensing.
The robot initializes itself in seek mode and takes autonomous action to find the devoid path. It has a wide range of temperature sensing and intensity detection capabilities. AVR studio 4 and ATMEL studio 6.1 were used for writing programs in Embedded C. Circuit simulation was done on Proteus, and a working prototype was developed.