I am a Silicon Architect at Google specializing in the architecture and power-performance co-optimization of next-generation AI Inference accelerators.
My journey in silicon architecture began with a Master's from IIT Dhanbad and a Ph.D. from the NeuRonICS Lab at IISc Bangalore. My doctoral research focused on breaking the Von Neumann bottleneck by designing brain-inspired, analog-mixed signal hardware and emerging in-memory computing architectures. This culminated in the successful design and tape-out of a fully analog AI accelerator, as well as exploring hybrid architectures compatible with novel 2D synaptic memory and planar CMOS technology.
Following my Ph.D., I joined Qualcomm as a Senior Lead Power and Performance Architect in the GPU IP team. There, I tackled complex hardware challenges to contribute to highly power-efficient and performant GPU cores for mobile and edge devices.
Today, I bring this deep expertise and full-stack modeling to Google. My current focus is architecting scalable, energy-efficient silicon for the next frontier of datacenter AI workloads.
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