Leveraging my Ph.D. in hardware-aware AI compute and Edge architectures from the Indian Institute of Science (IISc), NeuRonICS lab, I'm a Senior Lead for Power and Performance Architect in the GPU IP team at Qualcomm. My research focused on the intersection of hardware-friendly machine learning algorithms, high-performance machine learning computational accelerators (analog-mixed signal hardware), and emerging memory architectures for in-memory/near-memory computing.
During my Ph.D., I designed several novel computational systems for machine learning and edge computing tasks. These systems explored hybrid architectures compatible with both novel 2D synaptic memory and planar CMOS technology. Inspired by the brain, they all utilized in-memory/near-memory computing to overcome the Von Neumann bottleneck.
My dedication for tackling hardware challenges in machine learning and edge computing continues at Qualcomm. Here, I focus on developing power-efficient and high-performance GPU cores for mobile and embedded devices.
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