Designed a response plan based on ZigBee using SenScript in CupCarbon. The sensor nodes were clustered based on the range of values and the response plan was based on the A* algorithm. The system was evaluated by considering the figure of merits such as runtime, battery dissipation at the node level, and the number of lost messages.
Implemented machine learning algorithms such as linear regression, logistic regression, neural networks, random forest, and nearest neighbor, on MNIST database using TensorFlow library (Python).
Developed a temperature monitoring system with help of ESP8266 NodeMCU, DHT11 temperature sensor, Microsoft Azure and visualized the data using PowerBI. The MCU was programmed using DHT library in Arduino and the stream data analytics were performed using Azure.
A prediction based automated food monitoring system was implemented using Piezo-electric sensors and classifiers in WEKA. The weight of the food consumed was collected using piezo sensors connected to Arduino. The nutrition information available in USDA nutrient database was obtained using JAVA program and the nutrition of each meal was computed. The system efficiency was close to 98%.
This project involved analyzing various parameters such as kurtosis, energy, mean and so on, from publicly available data in Kaggle, to calculate human step length. With the help of WEKA, each of these parameters were classified and the significance of these parameters on handheld devices (smart-phones) was analyzed.
A menu-driven program was displayed on the LCD where the user can control through the switches. The significant options in the menu included joystick game, reading accelerometer, temperature readings, and LUX values.
A RISC processor that supports arithmetic, logical and data transfer was designed and verified using Verilog and System Verilog. UVM was used to build the test environment.
Designed an IoT based monitoring system to send temperature and humidity data from Raspberry Pi to a cloud application. This was achieved using Node-RED, SenseHAT and IBM BlueMix.
This project involved two phases. The first phase involved choosing better features for speech recognition and the second phase involved implementing SMO in FPGA. A wide comparison of sample size of input signals along with optimization algorithms and feature extraction methods were done. It was observed that the classification results for alphabets were better when a 1500 sample size per word was used after applying FFT to the input, when decomposition strategy of SVMlight was used for optimization. With respect to words,better classification results were obtained in general for SMO optimization especially when the input sample size was 39*120.The algorithm suggested (VAD-MFCC-SVM) yielded better results compared to previous speech recognition algorithms. Since SMO optimization yielded better results,Verilog implementation of this algorithm was done and the same was tested using FPGA. This analysis helped in understanding better algorithms for speech recognition along with a deeper understanding of optimization algorithms involved in support vector machines.
Two 4X4 arrays of 6Transistor SRAM cells were designed using 45nm technology in Cadence Virtuoso.In the first architecture two 2X4 Decoders were designed using NAND gates. The bit lines were charged to half of the Vdd supply and the Self timed Sense amplifier was used such that the sensing was activated only for the required period.In the second architecture , there was a reduction in the switching activity at each SRAM cell by providing separate read and write lines, such that a particular group of cells can be accessed by dividing the total number of lines into global and local word lines.The power consumption was almost double in the second architecture. Presented this paper in the 8th International Conference on Science,Engineering and Technology(SET),May 2014. TOOL: Cadence
This project is about implementing and analyzing the area and power consumption of multipliers such as Baugh Wooley,Wallace tree and braun multiplier in FIR architecture. The multipliers were designed using Verilog HDL and the power and area analysis was done using Quartus tool in DE1 board.
This project is about designing encoder and decoder modules in nano memories using LDPC codes in order to correct the errors.Presented this paper in the International Conference on Electrical Engineering and Computer Science,Hong Kong,December 2013.
Design of Network Interface Unit (NIU) and protocol for inter IP communication,Introduced SILENT encoders/decoders for power reduction. ASIC flow result: Achieved 22% power reduction for 90nm library cells using RTL Compiler and Physical design using the Cadence Encounter tool.