Embedded Files
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;;
;; msp430 include file generated by make_include.py
;; part of the naken_asm assembler
;;
;; Generated by: Michael Kohn (mike@mikekohn.net)
;; Input File: msp430g2x31.txt
;; Date: 2011-06-19 14:26
;; Parts: msp430x2xx (entire family)
;;
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;; push #4 and push #8 on cpu4 MSP430 have issues when using CG
.msp430_cpu4
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;; ADC10
ADC10SA equ 0x01bc ; ADC data transfer start address
ADC10CTL0 equ 0x01b0 ; ADC control 0
ADC10CTL1 equ 0x01b2 ; ADC control 1
ADC10MEM equ 0x01b4 ; ADC memory
SREF_0 equ 0x0000 ; Vr+ = Vcc and Vr- = Vss
SREF_1 equ 0x2000 ; Vr+ = Vref+ and Vr- = Vss
SREF_2 equ 0x4000 ; Vr+ = Veref+ and Vr- = Vss
SREF_3 equ 0x6000 ; Vr+ = Buffered Veref+ and Vr- = Vss
SREF_4 equ 0x8000 ; Vr+ = Vcc and Vr- = Vref- / Veref-
SREF_5 equ 0xa000 ; Vr+ = Vref+ and Vr- = Vref- / Veref-
SREF_6 equ 0xc000 ; Vr+ = Veref+ and Vr- = Vref- / Veref-
SREF_7 equ 0xe000 ; Vr+ = Buffered Veref+ and Vr- = Vref- / Veref-
ADC10SHT_0 equ 0x0000 ; 4 * ADC10CLKs
ADC10SHT_1 equ 0x0800 ; 8 * ADC10CLKs
ADC10SHT_2 equ 0x1000 ; 16 * ADC10CLKs
ADC10SHT_3 equ 0x1800 ; 64 * ADC10CLKs
ADC10SR equ 0x0400 ; ADC10 sampling rate
REFOUT equ 0x0200 ; reference output
REFBURST equ 0x0100 ; reference burst
MISC equ 0x0080 ; mutiple sample and conversion
REF2_5V equ 0x0040 ; reference generator voltage
REFON equ 0x0020 ; reference generator on
ADC10ON equ 0x0010 ; ADC10 on
ADC10IE equ 0x0008 ; ADC10 interrupt enable
ADC10IFG equ 0x0004 ; ADC10 interrupt flag
ENC equ 0x0002 ; enable conversion
ADC10SC equ 0x0001 ; start sample and conversion
INCH_0 equ 0x0000 ; input channel A0
INCH_1 equ 0x1000 ; input channel A1
INCH_2 equ 0x2000 ; input channel A2
INCH_3 equ 0x3000 ; input channel A3
INCH_4 equ 0x4000 ; input channel A4
INCH_5 equ 0x5000 ; input channel A5
INCH_6 equ 0x6000 ; input channel A6
INCH_7 equ 0x7000 ; input channel A7
INCH_8 equ 0x8000 ; VeREF+
INCH_9 equ 0x9000 ; VREF-/Veref-
INCH_10 equ 0xa000 ; temperature sensor
INCH_11 equ 0xb000 ; (Vcc-Vss)/2
INCH_12 equ 0xc000 ; (Vcc-Vss)/2, A12 on MSP430x22xx
INCH_13 equ 0xd000 ; (Vcc-Vss)/2, A13 on MSP430x22xx
INCH_14 equ 0xe000 ; (Vcc-Vss)/2, A14 on MSP430x22xx
INCH_15 equ 0xf000 ; (Vcc-Vss)/2, A15 on MSP430x22xx
SHS_0 equ 0x0000 ; sample-and-hold select ADC10SC
SHS_1 equ 0x0400 ; sample-and-hold Timer_A.OUT1
SHS_2 equ 0x0800 ; sample-and-hold Timer_A.OUT0
SHS_3 equ 0x0c00 ; sample-and-hold Timer_A.OUT2 (Timer_A.OUT1 on MSP430x20x2)
ADC10DF equ 0x0200 ; 2's complement data format (0 for straight binary)
ISSH equ 0x0100 ; sample-input signal inverted
ADC10DIV_0 equ 0x0000 ; /1 ADC clock divider
ADC10DIV_1 equ 0x0020 ; /2 ADC clock divider
ADC10DIV_2 equ 0x0040 ; /3 ADC clock divider
ADC10DIV_3 equ 0x0060 ; /4 ADC clock divider
ADC10DIV_4 equ 0x0080 ; /5 ADC clock divider
ADC10DIV_5 equ 0x00a0 ; /6 ADC clock divider
ADC10DIV_6 equ 0x00c0 ; /7 ADC clock divider
ADC10DIV_7 equ 0x00e0 ; /8 ADC clock divider
ADC10SSEL_0 equ 0x0000 ; ADC10OSC
ADC10SSEL_1 equ 0x0008 ; ACLK
ADC10SSEL_2 equ 0x0010 ; MCLK
ADC10SSEL_3 equ 0x0018 ; SMCLK
CONSEQ_0 equ 0x0000 ; single channel conversion
CONSEQ_1 equ 0x0002 ; sequence of channels
CONSEQ_2 equ 0x0004 ; repeat single channel
CONSEQ_3 equ 0x0006 ; repeqt sequence of channels
ADC10BUSY equ 0x0001 ; a sequence, sample, or conversion is active
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Timer_A
TACCR1 equ 0x0174 ; Capture/compare register
TACCR0 equ 0x0172 ; Capture/compare register
TAR equ 0x0170 ; Timer_A register
TACCTL0 equ 0x0162 ; Capture/compare control
TACCTL1 equ 0x0164 ; Capture/compare control
TACTL equ 0x0160 ; Timer_A control
TAIV equ 0x012e ; Timer_A interrupt vector
TASSEL_0 equ 0 ; TACLK
TASSEL_1 equ 256 ; ACLK
TASSEL_2 equ 512 ; SMCLK
TASSEL_3 equ 768 ; INCLK
ID_0 equ 0 ; div by 1
ID_1 equ 64 ; div by 2
ID_2 equ 128 ; div by 4
ID_3 equ 192 ; div by 8
MC_0 equ 0 ; timer is halted
MC_1 equ 16 ; timer counts up to TACCR0
MC_2 equ 32 ; timer counts up to 0xffff
MC_3 equ 48 ; up/down timer counts up to TACCR0 then down to 0x0000
TACLR equ 4 ; Timer_A clear
TAIE equ 2 ; interrupt enable
TAIFG equ 1 ; timer interrupt flag
CM_0 equ 0x0000 ; no capture
CM_1 equ 0x4000 ; capture on rising edge
CM_2 equ 0x8000 ; capture on falling edge
CM_3 equ 0xc000 ; capture on both rising and falling edges
CCIS_0 equ 0x0000 ; capture from CCIxA
CCIS_1 equ 0x1000 ; capture from CCIxB
CCIS_2 equ 0x2000 ; capture from GND
CCIS_3 equ 0x3000 ; capture from Vcc
SCS equ 0x0800 ; synchronous capture
SCCI equ 0x0400 ; synchronize capture/compare input
CAP equ 0x0100 ; capture mode
OUTMOD_0 equ 0x0000 ; OUT bit value
OUTMOD_1 equ 0x0020 ; Set
OUTMOD_2 equ 0x0040 ; Toggle/reset
OUTMOD_3 equ 0x0060 ; Set/reset
OUTMOD_4 equ 0x0080 ; Toggle
OUTMOD_5 equ 0x00a0 ; Reset
OUTMOD_6 equ 0x00c0 ; Toggle/set
OUTMOD_7 equ 0x00e0 ; Reset/set
CCIE equ 0x0010 ; capture/compare interrupt enable
CCI equ 0x0008 ; capture/compare input
OUT equ 0x0004 ; output high
COV equ 0x0002 ; capture overflow
CCIFG equ 0x0001 ; interrupt pending
;; Timer_B
TBCTL equ 0x180
TBR equ 0x190
TBCCTL0 equ 0x182
TBCCR0 equ 0x192
TBCCTL1 equ 0x184
TBCCR1 equ 0x194
TBCCTL2 equ 0x186
TBCCR2 equ 0x196
TBCCTL3 equ 0x188
TBCCR3 equ 0x198
TBCCTL4 equ 0x18a
TBCCR4 equ 0x19a
TBCCTL5 equ 0x18c
TBCCR5 equ 0x19c
TBCCTL6 equ 0x18e
TBCCR6 equ 0x19e
TBIV equ 0x11e
TBCLGRP_0 equ 0x0000
TBCLGRP_1 equ 0x2000
TBCLGRP_2 equ 0x4000
TBCLGRP_3 equ 0x6000
CNTL_0 equ 0x0000
CNTL_1 equ 0x0800
CNTL_2 equ 0x1000
CNTL_3 equ 0x1800
TBSSEL_0 equ 0x0000
TBSSEL_1 equ 0x0100
TBSSEL_2 equ 0x0200
TBSSEL_3 equ 0x0300
TBCLR equ 0x4
TBIE equ 0x2
TBIFG equ 0x1
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Flash Memory
FCTL4 equ 0x01be ; Flash control 4
FCTL3 equ 0x012c ; Flash control 3
FCTL2 equ 0x012a ; Flash control 2
FCTL1 equ 0x0128 ; Flash control 1
FWKEY equ 0xa500
FRKEY equ 0x9600
BLKWRT equ 0x0080
WRT equ 0x0040
EEIEX equ 0x0010
EEI equ 0x0008
MERAS equ 0x0004
ERASE equ 0x0002
FSSEL_0 equ 0x00
FSSEL_1 equ 0x40
FSSEL_2 equ 0x80
FSSEL_3 equ 0xc0
FAIL equ 0x80
LOCKA equ 0x40
EMEX equ 0x20
LOCK equ 0x10
WAIT equ 0x08
ACCVIFG equ 0x04
KEYV equ 0x02
BUSY equ 0x01
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Watchdog Timer+
WDTCTL equ 0x0120 ; Watchdog/timer control
WDTPW equ 0x5a00
WDTHOLD equ 0x0080
WDTNMIES equ 0x0040
WDTNMI equ 0x0020
WDTTMSEL equ 0x0010
WDTCNTCL equ 0x0008
WDTSSEL equ 0x0004
WDTIS0 equ 0x0000
WDTIS1 equ 0x0001
WDTIS2 equ 0x0002
WDTIS3 equ 0x0003
NMIIE equ 0x10
WDTIE equ 0x01
NMIFG equ 0x10
WDTIFG equ 0x01
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; ADC10
ADC10AE0 equ 0x004a ; ADC analog enable
ADC10AE1 equ 0x004b ; ADC analog enable
ADC10DTC1 equ 0x0049 ; ADC data transfer control 1
ADC10DTC0 equ 0x0048 ; ADC data transfer control 0
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; USI
USICTL0 equ 0x0078 ; USI control 0
USICTL1 equ 0x0079 ; USI control 1
USICKCTL equ 0x007a ; USI clock control
USICNT equ 0x007b ; USI bit counter
USISRL equ 0x007c ; USI shift register low
USISRH equ 0x007d ; USI shift register high
; word access defines
USICTL equ 0x0078 ; USI control
USICCTL equ 0x007a ; USI clock and counter control register
USISR equ 0x007c ; USI shift register
USIPE7 equ 128
USIPE6 equ 64
USIPE5 equ 32
USILSB equ 16
USIMST equ 8
USIGE equ 4
USIOE equ 2
USISWRST equ 1
USICKPH equ 128
USII2C equ 64
USISTTIE equ 32
USIIE equ 16
USIAL equ 8
USISTP equ 4
USISTTIFG equ 2
USIIFG equ 1
USIDIV_0 equ 0x00
USIDIV_1 equ 0x20
USIDIV_2 equ 0x40
USIDIV_3 equ 0x60
USIDIV_4 equ 0x80
USIDIV_5 equ 0xa0
USIDIV_6 equ 0xc0
USIDIV_7 equ 0xe0
USISSEL_0 equ 0x00
USISSEL_1 equ 0x04
USISSEL_2 equ 0x08
USISSEL_3 equ 0x0c
USISSEL_4 equ 0x10
USISSEL_5 equ 0x14
USISSEL_6 equ 0x18
USISSEL_7 equ 0x1c
USICKPL equ 2
USISWCLK equ 1
USISCLREL equ 128
USI16B equ 64
USIIFGCC equ 32
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; USCI_A0
UCA0CTL0 equ 0x60 ; USCI_A0 control register 0
UCA0CTL1 equ 0x61 ; USCI_A0 control register 1
UCA0BR0 equ 0x62 ; USCI_A0 baud rate control register 0
UCA0BR1 equ 0x63 ; USCI_A0 baud rate control register 1
UCA0MCTL equ 0x64 ; USCI_A0 modulation control register
UCA0STAT equ 0x65 ; USCI_A0 status register
UCA0RXBUF equ 0x66 ; USCI_A0 receive buffer register
UCA0TXBUF equ 0x67 ; USCI_A0 transmit buffer register
UCA0ABCTL equ 0x5d ; USCI_A0 Auto baud control register
UCA0IRTCTL equ 0x5e ; USCI_A0 IrDA transmit control register
UCA0IRRCTL equ 0x5f ; USCI_A0 IrDA receive control register
UCB0CTL0 equ 0x68 ; USCI_B0 control register 0
UCB0CTL1 equ 0x69 ; USCI_B0 control register 1
UCB0BR0 equ 0x6a ; USCI_B0 baud rate control register 0
UCB0BR1 equ 0x6b ; USCI_B0 baud rate control register 1
UCB0STAT equ 0x6d ; USCI_B0 status register
UCB0RXBUF equ 0x6e ; USCI_B0 receive buffer register
UCB0TXBUF equ 0x6f ; USCI_B0 transmit buffer register
UCB0I2CIE equ 0x6c ; USCI_B0 I2C interrupt enable register
UCB0I2COA equ 0x118 ; USCI_B0 I2C own address register
UCB0I2CSA equ 0x11a ; USCI_B0 I2C slave address register
UCPEN equ 128
UCPAR equ 64
UCMSB equ 32
UC7BIT equ 16
UCSPB equ 8
UCMODE_0 equ 0
UCMODE_1 equ 2
UCMODE_2 equ 4
UCMODE_3 equ 6
USYNC equ 1
UCNACKIE equ 0x08
UCSTPIE equ 0x04
UCSTTIE equ 0x02
UCALIE equ 0x01
UCSCLLOW equ 0x40
UCGC equ 0x20
UCBBUSY equ 0x10
UCNACKIFG equ 0x08
UCSTPIFG equ 0x04
UCSTTIFG equ 0x02
UCALIFG equ 0x01
UCSSEL_0 equ 0x00
UCSSEL_1 equ 0x40
UCSSEL_2 equ 0x80
UCSSEL_3 equ 0xc0
UCTR equ 0x10
UCTXNACK equ 0x08
UCTXSTP equ 0x04
UCTXSTT equ 0x02
UCRXEIE equ 0x20
UCBRKIE equ 0x10
UCDORM equ 0x08
UCTXADDR equ 0x04
UCTXBRK equ 0x02
UCSWRST equ 0x01
UCBRF_0 equ 0x00
UCBRF_1 equ 0x10
UCBRF_2 equ 0x20
UCBRF_3 equ 0x30
UCBRF_4 equ 0x40
UCBRF_5 equ 0x50
UCBRF_6 equ 0x60
UCBRF_7 equ 0x70
UCBRF_8 equ 0x80
UCBRF_9 equ 0x90
UCBRF_10 equ 0xa0
UCBRF_11 equ 0xb0
UCBRF_12 equ 0xc0
UCBRF_13 equ 0xd0
UCBRF_14 equ 0xe0
UCBRF_15 equ 0xf0
UCBRS_0 equ 0x00
UCBRS_1 equ 0x02
UCBRS_2 equ 0x04
UCBRS_3 equ 0x06
UCBRS_4 equ 0x08
UCBRS_5 equ 0x0a
UCBRS_6 equ 0x0c
UCBRS_7 equ 0x0e
UCOS16 equ 0x01
UCLISTEN equ 0x80
UCFE equ 0x40
UCOE equ 0x20
UCPE equ 0x10
UCBRK equ 0x08
UCRXERR equ 0x04
UCADDR equ 0x02
UCIDLE equ 0x02
UCBUSY equ 0x01
UCIRTXPL_0 equ 0x00
UCIRTXPL_1 equ 0x04
UCIRTXPL_2 equ 0x08
UCIRTXPL_3 equ 0x0c
UCIRTXPL_4 equ 0x10
UCIRTXPL_5 equ 0x14
UCIRTXPL_6 equ 0x18
UCIRTXPL_7 equ 0x1c
UCIRTXPL_8 equ 0x20
UCIRTXPL_9 equ 0x24
UCIRTXPL_10 equ 0x28
UCIRTXPL_11 equ 0x2c
UCIRTXPL_12 equ 0x30
UCIRTXPL_13 equ 0x34
UCIRTXPL_14 equ 0x38
UCIRTXPL_15 equ 0x3c
UCIRTXPL_16 equ 0x40
UCIRTXPL_17 equ 0x44
UCIRTXPL_18 equ 0x48
UCIRTXPL_19 equ 0x4c
UCIRTXPL_20 equ 0x50
UCIRTXPL_21 equ 0x54
UCIRTXPL_22 equ 0x58
UCIRTXPL_23 equ 0x5c
UCIRTXPL_24 equ 0x60
UCIRTXPL_25 equ 0x64
UCIRTXPL_26 equ 0x68
UCIRTXPL_27 equ 0x6c
UCIRTXPL_28 equ 0x70
UCIRTXPL_29 equ 0x74
UCIRTXPL_30 equ 0x78
UCIRTXPL_31 equ 0x7c
UCIRTXPL_32 equ 0x80
UCIRTXPL_33 equ 0x84
UCIRTXPL_34 equ 0x88
UCIRTXPL_35 equ 0x8c
UCIRTXPL_36 equ 0x90
UCIRTXPL_37 equ 0x94
UCIRTXPL_38 equ 0x98
UCIRTXPL_39 equ 0x9c
UCIRTXPL_40 equ 0xa0
UCIRTXPL_41 equ 0xa4
UCIRTXPL_42 equ 0xa8
UCIRTXPL_43 equ 0xac
UCIRTXPL_44 equ 0xb0
UCIRTXPL_45 equ 0xb4
UCIRTXPL_46 equ 0xb8
UCIRTXPL_47 equ 0xbc
UCIRTXPL_48 equ 0xc0
UCIRTXPL_49 equ 0xc4
UCIRTXPL_50 equ 0xc8
UCIRTXPL_51 equ 0xcc
UCIRTXPL_52 equ 0xd0
UCIRTXPL_53 equ 0xd4
UCIRTXPL_54 equ 0xd8
UCIRTXPL_55 equ 0xdc
UCIRTXPL_56 equ 0xe0
UCIRTXPL_57 equ 0xe4
UCIRTXPL_58 equ 0xe8
UCIRTXPL_59 equ 0xec
UCIRTXPL_60 equ 0xf0
UCIRTXPL_61 equ 0xf4
UCIRTXPL_62 equ 0xf8
UCIRTXPL_63 equ 0xfc
UCIRTXCLK equ 0x02
UCIREN equ 0x01
UCIRRXFL_0 equ 0x00
UCIRRXFL_1 equ 0x04
UCIRRXFL_2 equ 0x08
UCIRRXFL_3 equ 0x0c
UCIRRXFL_4 equ 0x10
UCIRRXFL_5 equ 0x14
UCIRRXFL_6 equ 0x18
UCIRRXFL_7 equ 0x1c
UCIRRXFL_8 equ 0x20
UCIRRXFL_9 equ 0x24
UCIRRXFL_10 equ 0x28
UCIRRXFL_11 equ 0x2c
UCIRRXFL_12 equ 0x30
UCIRRXFL_13 equ 0x34
UCIRRXFL_14 equ 0x38
UCIRRXFL_15 equ 0x3c
UCIRRXFL_16 equ 0x40
UCIRRXFL_17 equ 0x44
UCIRRXFL_18 equ 0x48
UCIRRXFL_19 equ 0x4c
UCIRRXFL_20 equ 0x50
UCIRRXFL_21 equ 0x54
UCIRRXFL_22 equ 0x58
UCIRRXFL_23 equ 0x5c
UCIRRXFL_24 equ 0x60
UCIRRXFL_25 equ 0x64
UCIRRXFL_26 equ 0x68
UCIRRXFL_27 equ 0x6c
UCIRRXFL_28 equ 0x70
UCIRRXFL_29 equ 0x74
UCIRRXFL_30 equ 0x78
UCIRRXFL_31 equ 0x7c
UCIRRXFL_32 equ 0x80
UCIRRXFL_33 equ 0x84
UCIRRXFL_34 equ 0x88
UCIRRXFL_35 equ 0x8c
UCIRRXFL_36 equ 0x90
UCIRRXFL_37 equ 0x94
UCIRRXFL_38 equ 0x98
UCIRRXFL_39 equ 0x9c
UCIRRXFL_40 equ 0xa0
UCIRRXFL_41 equ 0xa4
UCIRRXFL_42 equ 0xa8
UCIRRXFL_43 equ 0xac
UCIRRXFL_44 equ 0xb0
UCIRRXFL_45 equ 0xb4
UCIRRXFL_46 equ 0xb8
UCIRRXFL_47 equ 0xbc
UCIRRXFL_48 equ 0xc0
UCIRRXFL_49 equ 0xc4
UCIRRXFL_50 equ 0xc8
UCIRRXFL_51 equ 0xcc
UCIRRXFL_52 equ 0xd0
UCIRRXFL_53 equ 0xd4
UCIRRXFL_54 equ 0xd8
UCIRRXFL_55 equ 0xdc
UCIRRXFL_56 equ 0xe0
UCIRRXFL_57 equ 0xe4
UCIRRXFL_58 equ 0xe8
UCIRRXFL_59 equ 0xec
UCIRRXFL_60 equ 0xf0
UCIRRXFL_61 equ 0xf4
UCIRRXFL_62 equ 0xf8
UCIRRXFL_63 equ 0xfc
UCIRRXPL equ 0x02
UCIRRXFE equ 0x01
UCDELIM_0 equ 0x00
UCDELIM_1 equ 0x10
UCDELIM_2 equ 0x20
UCDELIM_3 equ 0x30
UCSTOE equ 0x08
UCBTOE equ 0x04
UCABDEN equ 0x01
UCA0TXIE equ 0x02
UCA0RXIE equ 0x01
UCA0TXIFG equ 0x02
UCA0RXIFG equ 0x01
UCCKPH equ 0x80
UCCKPL equ 0x40
;UCMSB equ 0x20
;UC7BIT equ 0x10
UCMST equ 0x08
;UCMODE_0 equ 0x00
;UCMODE_1 equ 0x02
;UCMODE_2 equ 0x04
;UCMODE_3 equ 0x06
UCSYNC equ 0x01
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; USCI_A1
UCA1CTL0 equ 0xd0 ; USCI_A1 control register 0
UCA1CTL1 equ 0xd1 ; USCI_A1 control register 1
UCA1BR0 equ 0xd2 ; USCI_A1 baud rate control register 0
UCA1BR1 equ 0xd3 ; USCI_A1 baud rate control register 1
UCA10MCTL equ 0xd4 ; USCI_A1 modulation control register
UCA1STAT equ 0xd5 ; USCI_A1 status register
UCA1RXBUF equ 0xd6 ; USCI_A1 receive buffer register
UCA1TXBUF equ 0xd7 ; USCI_A1 transmit buffer register
UCA1ABCTL equ 0xcd ; USCI_A1 auto baud control register
UCA1IRTCTL equ 0xce ; USCI_A1 IrDA transmit control register
UCA1IRRCTL equ 0xcf ; USCI_A1 IrDA receive control register
UCI1E equ 0x06 ; USCI_A1/B1 interrupt enable register
UC1FG equ 0x07 ; USCI_A1/B1 interrupt flag register
UCA1TXIE equ 0x02
UCA1RXIE equ 0x01
UCA1TXIFG equ 0x02
UCA1RXIFG equ 0x01
UCB0TXIFG equ 0x08
UCB0RXIFG equ 0x04
UCB1TXIFG equ 0x08
UCB1RXIFG equ 0x04
UCB0TXIE equ 0x08
UCB0RXIE equ 0x04
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Basic Clock System+
BCSCTL3 equ 0x0053 ; Basic clock system control 3
BCSCTL2 equ 0x0058 ; Basic clock system control 2
BCSCTL1 equ 0x0057 ; Basic clock system control 1
DCOCTL equ 0x0056 ; DCO clock frequency control
DCO_0 equ 0x00
DCO_1 equ 0x20
DCO_2 equ 0x40
DCO_3 equ 0x60
DCO_4 equ 0x80
DCO_5 equ 0xa0
DCO_6 equ 0xc0
DCO_7 equ 0xe0
MOD_0 equ 0x00
MOD_1 equ 0x01
MOD_2 equ 0x02
MOD_3 equ 0x03
MOD_4 equ 0x04
MOD_5 equ 0x05
MOD_6 equ 0x06
MOD_7 equ 0x07
MOD_8 equ 0x08
MOD_9 equ 0x09
MOD_10 equ 0x0a
MOD_11 equ 0x0b
MOD_12 equ 0x0c
MOD_13 equ 0x0d
MOD_14 equ 0x0e
MOD_15 equ 0x0f
MOD_16 equ 0x10
MOD_17 equ 0x11
MOD_18 equ 0x12
MOD_19 equ 0x13
MOD_20 equ 0x14
MOD_21 equ 0x15
MOD_22 equ 0x16
MOD_23 equ 0x17
MOD_24 equ 0x18
MOD_25 equ 0x19
MOD_26 equ 0x1a
MOD_27 equ 0x1b
MOD_28 equ 0x1c
MOD_29 equ 0x1d
MOD_30 equ 0x1e
MOD_31 equ 0x1f
XT2OFF equ 128 ; turn of XT2 oscillator
XTS equ 64 ; high freq mode
DIVA_0 equ 0x00 ; /1 for ACLK
DIVA_1 equ 0x10 ; /2 for ACLK
DIVA_2 equ 0x20 ; /4 for ACLK
DIVA_3 equ 0x30 ; /8 for ACLK
RSEL_0 equ 0x00
RSEL_1 equ 0x01
RSEL_2 equ 0x02
RSEL_3 equ 0x03
RSEL_4 equ 0x04
RSEL_5 equ 0x05
RSEL_6 equ 0x06
RSEL_7 equ 0x07
RSEL_8 equ 0x08
RSEL_9 equ 0x09
RSEL_10 equ 0x0a
RSEL_11 equ 0x0b
RSEL_12 equ 0x0c
RSEL_13 equ 0x0d
RSEL_14 equ 0x0e
RSEL_15 equ 0x0f
SELM_0 equ 0 ; MCLK is DOCLK
SELM_1 equ 64 ; MCLK is DCOLK
SELM_2 equ 128 ; MCLK is XT2CLK, LFXT1CLK, or VLOCLK
SELM_3 equ 192 ; MCLK is LFX1CLK or VLOCLK
DIVM_0 equ 0x00 ; /1 for MCLK
DIVM_1 equ 0x10 ; /2 for MCLK
DIVM_2 equ 0x20 ; /4 for MCLK
DIVM_3 equ 0x30 ; /8 for MCLK
SELS equ 8 ; XT2CLK or LFX1CLK or VLOCLK
DIVS_0 equ 0x00 ; /1 for SMCLK
DIVS_1 equ 0x02 ; /2 for SMCLK
DIVS_2 equ 0x04 ; /4 for SMCLK
DIVS_3 equ 0x06 ; /8 for SMCLK
DCOR equ 1 ; external resistor
XT2S_0 equ 0x00
XT2S_1 equ 0x40
XT2S_2 equ 0x80
XT2S_3 equ 0xc0
LFXT1S_0 equ 0x00
LFXT1S_1 equ 0x10
LFXT1S_2 equ 0x20
LFXT1S_3 equ 0x30
XCAP_0 equ 0x00
XCAP_1 equ 0x04
XCAP_2 equ 0x08
XCAP_3 equ 0x0c
XT2OF equ 0x02
LFXT1OF equ 0x01
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Port P1
P1REN equ 0x0027 ; Port P1 resistor enable
P1SEL equ 0x0026 ; Port P1 selection
P1IE equ 0x0025 ; Port P1 interrupt enable
P1IES equ 0x0024 ; Port P1 interrupt edge select
P1IFG equ 0x0023 ; Port P1 interrupt flag
P1DIR equ 0x0022 ; Port P1 direction
P1OUT equ 0x0021 ; Port P1 output
P1IN equ 0x0020 ; Port P1 input
P1SEL2 equ 0x0041 ; Port P1 selection 2
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Port P2
P2REN equ 0x002f ; Port P2 resistor enable
P2SEL equ 0x002e ; Port P2 selection
P2IE equ 0x002d ; Port P2 interrupt enable
P2IES equ 0x002c ; Port P2 interrupt edge select
P2IFG equ 0x002b ; Port P2 interrupt flag
P2DIR equ 0x002a ; Port P2 direction
P2OUT equ 0x0029 ; Port P2 output
P2IN equ 0x0028 ; Port P2 input
P2SEL2 equ 0x0042 ; Port P1 selection 2
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;; Port P3
P3IN equ 0x18 ; Input
P3OUT equ 0x19 ; Output
P3DIR equ 0x1a ; Direction
P3SEL equ 0x1b ; Port Select
P3SEL2 equ 0x43 ; Port Select 2
P3REN equ 0x10 ; Resistor Enable
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;; Port P4
P4IN equ 0x1c ; Input
P4OUT equ 0x1d ; Output
P4DIR equ 0x1e ; Direction
P4SEL equ 0x1f ; Port Select
P4SEL2 equ 0x44 ; Port Select 2
P4REN equ 0x11 ; Resistor Enable
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;; Port P5
P5IN equ 0x30 ; Input
P5OUT equ 0x31 ; Output
P5DIR equ 0x32 ; Direction
P5SEL equ 0x33 ; Port Select
P5SEL2 equ 0x45 ; Port Select 2
P5REN equ 0x12 ; Resistor Enable
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;; Port P6
P6IN equ 0x34 ; Input
P6OUT equ 0x35 ; Output
P6DIR equ 0x36 ; Direction
P6SEL equ 0x37 ; Port Select
P6SEL2 equ 0x46 ; Port Select 2
P6REN equ 0x13 ; Resistor Enable
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;; Port P7
P7IN equ 0x38 ; Input
P7OUT equ 0x3a ; Output
P7DIR equ 0x3c ; Direction
P7SEL equ 0x3e ; Port Select
P7SEL2 equ 0x47 ; Port Select 2
P7REN equ 0x14 ; Resistor Enable
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;; Port P8
P8IN equ 0x39 ; Input
P8OUT equ 0x3b ; Output
P8DIR equ 0x3d ; Direction
P8SEL equ 0x3f ; Port Select
P8SEL2 equ 0x48 ; Port Select 2
P8REN equ 0x15 ; Resistor Enable
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;; SFR Special Function
IFG2 equ 0x0003 ; SFR interrupt flag 2
IFG1 equ 0x0002 ; SFR interrupt flag 1
IE2 equ 0x0001 ; SFR interrupt enable 2
IE1 equ 0x0000 ; SFR interrupt enable 1
OSCOFF equ 32
OFIFG equ 2
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;; Comparitor_A+
CAPD equ 0x5b
CACTL2 equ 0x5a
CACTL1 equ 0x59
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