Abstract: The continuing evolution of silicon CMOS technology is clearly approaching some important physical limits. Since roughly 2003, the increasing inability to reduce supply voltages without adversely impacting performance, combined with physical and economic constraints on power density and total power, has forced designers to limit clock frequencies even as devices have continued to shrink. Either the device physics or the system architecture must change in a fundamental way if computing is to escape this power-performance bottleneck. Thus the exploration of entirely new energy-efficient devices and architectures for computing is essential if we are to take high performance computing well beyond Exascale. Today, device research programs and directions started over 10 years ago are beginning to bear fruit, with the latest device demonstrations opening a new low-power design space which is inaccessible to conventional FETs. At the same time, research in new architectures, particularly artificial neural networks, is also exploding. At the leading edge, some researchers are beginning to focus on co-optimization of new devices and new architectures for computing.
Bio: THOMAS THEIS is Executive Director of the Columbia Nano Initiative (CNI) and Professor in Electrical Engineering in the Fu Foundation School of Engineering, Arts and Sciences. He joined IBM at the T.J. Watson Research Center in 1978 to study electronic properties of materials, and held various senior management and executive positions from 1984 through 2015. In the late 1990’s, as Senior Manager, Silicon Science and Technology, he coordinated the transfer of copper interconnection technology from IBM Research to the IBM Microelectronics Division. The replacement of aluminum chip wiring by copper was an industry first, the biggest change in chip wiring technology in thirty years, and involved close collaboration between research, product development, and manufacturing organizations. As IBM’s strategist for exploratory research worldwide from 1998 to 2012 and as Director, Physical Sciences from 1998 to 2010, he conceived and initiated successful research programs in silicon nanophotonics and Josephson junction-based quantum computing, and championed research in nanoelectronics, exploratory memory devices, and applications of information technology to address societal needs in energy, infrastructure, and the environment. From 2010 – 2012, as Program Manager, New Devices and Architectures for Computing, he organized new research projects aimed at greatly improved energy-efficiency in future computing systems. On assignment from IBM to the Semiconductor Research Corporation (SRC) from 2012 – 2016, he led SRC’s Nanoelectronics Research Initiative, a private-public partnership funding university research aimed at new devices and circuits for computing. He joined Columbia University in April of 2016 to manage and lead CNI operations and work with faculty and university research offices to identify and develop concepts for major new research programs. CNI’s shared research facilities provide critical support for Columbia’s research initiatives in Nanoscale Science and Engineering.
Abstract: As microelectronics technology nears the end of exponential growth over time, known as Moore’s law, there is a renewed interest in new computing paradigms such as quantum computing. A key step in the roadmap to build a scientifically or commercially useful quantum computer will be to demonstrate its exponentially growing computing power. I will explain how a 7 by 7 array of superconducting xmon qubits with nearest-neighbor coupling, and with programmable single- and two-qubit gate with errors of about 0.2%, can execute a modest depth quantum computation that fully entangles the 49 qubits. Sampling of the resulting output can be checked against a classical simulation to demonstrate proper operation of the quantum computer and compare its system error rate with predictions. With a computation space of 2^49 = 5 x 10^14 states, the quantum computation can only be checked using the biggest supercomputers. I will show experimental data towards this demonstration from a 9 qubit adjustable-coupler “gmon” device, which implements the basic sampling algorithm of quantum supremacy for a computational (Hilbert) space of about 500. We plan to begin testing a 49 qubit device by the end of 2017.
Bio: John Martinis attended U.C. Berkeley from 1976 to 1987. His PhD thesis was a pioneering demonstration of quantum-bit states in superconductors. After postdoctoral research at CEA in France, he joined NIST Boulder where he developed electron counting devices and x-ray microcalorimeters. In 2004 he moved to U.C. Santa Barbara where he continued work on quantum computation. In 2014 he was awarded the London Prize for low-temperature physics research. In 2014 he joined the Google quantum-AI team and heads the hardware effort to build a useful quantum computer.