Product Information

A 4-inch silicon (100) wafer comprises 36 chips (1 cm × 1 cm each), with each chip containing 100 nMOSFETs. The overall fabrication yield is approximately 70 %. Prior to shipment, we perform in-house re-measurements of the ID–VG and ID–VD characteristics to inspect for any defective devices. Additionally, the locations of good dies are briefly screened and provided along with the samples for your convenience. 

Device I: Silicon nMOSFETs (SiO₂ Gate Dielectric)

• Parametric Information: VT ≈ - 0.1 V, SS ≈ 130 mV/dec

• Device Size: L: 5-50 μm (interval 5 μm), W: 190-280 μm (interval 10 μm), EOT = 10 nm

• Materials: Si, poly-Si, SiO2

• Wafer Price (including VAT): ₩ 3,300,000 (USD 2,700) per 4" wafer

• Die Price (including VAT): ₩ 330,000 (USD 270) per die

• References for Detailed Device Information:

   [1] M.-W. Kim et al., Semicond. Sci. Technol., vol. xx, no. x,  pp. xxxx-xxxx, in press. [ Website ] 

   [2] E.-C. Yun et al., IEEE Trans. Electron Devices, vol. xx, no. x,  pp. xxxx-xxxx, in press. [ Website ] 

   [3] J.-W. Yeon et al., IEEE Trans. Device Mater. Reliab., vol. 24, no. 4,  pp. 618-623, Dec. 2024. [ Website ]  

   [4] T.-H. Kil, et al., IEEE Trans. Electron Devices,  vol. 71, no. 9,  pp. 5177-5181, Sept. 2024. [ Website ]  

   [5] T.-H. Kil et al., IEEE Trans. Electron Devices,  vol. 71, no. 2,  pp. 1078–1083, Feb. 2024.  [ Website ] 

   [6] D.-H. Jung et al., IEEE Trans. Electron Devices, vol. 71, no. 1,  pp. 425–430, Jan. 2024. [ Website ] 

   [7] D.-H. Jung et al., Microelectron. Reliab., vol. 151, no. 115276, Dec. 2023. [ Website ] 

   [8] D.-H. Wang et al., IEEE Trans. Device Mater. Reliab., vol. 23, no. 2, pp. 297–301, Jun. 2023. [ Website ] 

   [9] J.-Y. Ku et al., IEEE Trans. Device Mater. Reliab., vol. 23, no. 3, pp. 276–280, Jun. 2023. [ Website ] 

   [10] J.-M. Yu et al., Solid-State Electron., vol. 197, no. 108421, Nov. 2022. [ Website ]  

   [11] D.-H. Jung et al., IEEE Trans. Device Mater. Reliab., vol. 22, no. 3, pp. 457–460, Sept. 2022. [ Website ]  

   [12] D.-H. Wang et al., Materials, vol. 15, no. 5, p. 1960, Mar. 2022. [ Website ]  

Device II: Silicon nMOSFETs (HKMG)

• Parametric Information: VT ≈ 0.3 V, SS ≈ 90 mV/dec

• Device Size: L: 5-10 μm (interval 5 μm), W: 80-120 μm (interval 20 μm), EOT = 3 nm (HKMG)

• Materials: Si, poly-Si, SiO2, HfO2, Al, TiN

• Wafer Price (including VAT): ₩ 9,900,000 (USD 8,100) per 4" wafer

• Die Price (including VAT): ₩ 990,000 (USD 810) per die

• References for Detailed Device Information:

[1] S.-J. Jeon et al., Semicond. Sci. Technol. vol. 40, no. 8,  pp. 1-5, Aug. 2025. [ Website ] 

    [2] T.-H. Kil et al., IEEE J. Electron Devices Soc., vol. 12, no. 1,  pp. 1030-1033, Dec. 2024. [ Website ]