Publications

Journals

· Shiann-Rong Kuang, Chih-Yuan Liang, and I-Ping Tseng, “A Low-Power Codeword-Based Viterbi Decoder with Fine-Grained Error Detection and Correction Techniques,” accepted by Arabian Journal for Science and Engineering, July 2017. 

· Shiann-Rong Kuang, Chih-Yuan Liang, and Ming-Fong Chang, “A Multi-functional Multi-precision 4D Dot Product Unit with SIMD Architecture,” Arabian Journal for Science and Engineering, Vol. 41, No. 8, pp. 3139–3151, August 2016. 

· Shiann-Rong Kuang, Chih-Yuan Liang, and Chun-Chi Chen, “An Efficient Radix-4 Scalable Architecture for Montgomery Modular Multiplication,” IEEE Transactions on Circuits and Systems Part II: Express Briefs, Vol. 63, No. 6, pp. 568–572, June 2016. 

· Shiann-Rong Kuang, Kun-Yi Wu, and Ren-Yao Lu, “Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, No. 2, pp.434–443, February 2016. 

· S.-R. Kuang and K.-Y. Wu, “Low-Energy Instruction Precision Assignment for Multi-Mode Multiplier under Accuracy and Performance Constraints,” Arabian Journal for Science and Engineering, Vol. 40, No. 3, pp.787–798, March 2015. 

· Shiann-Rong Kuang, Kun-Yi Wu, Bao-Chen Ke, Jia-Huei Yeh, and Hao-Yi Jheng, “Efficient architecture and hardware implementation of hybrid fuzzy-Kalman filter for workload prediction,” Integration, the VLSI Journal, Vol. 47, No. 4, pp. 408–416, September 2014. 

· Shiann-Rong Kuang, Jiun-Ping Wang, Kai-Cheng Chang, and Huan-Wei Hsu, “Energy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 11, pp.1999–2009, November 2013.  

· Kun-Yi Wu, Shiann-Rong Kuang, and Kee-Khuan Yu, “An Exact Method for Estimating Maximum Errors of Multi-mode Floating-point Iterative Booth Multiplier,” International Journal of Computational Science and Engineering, Vol. 8, No. 4, pp. 306–315, October 2013. 

· Shiann-Rong Kuang, Kun-Yi Wu and Kee-Khuan Yu, "Energy-Efficient Multiple-Precision Floating-Point Multiplier for Embedded Applications," Journal of Signal Processing Systems, Vol. 72, No. 1, pp. 43–55, July 2013. 

· Jiun-Ping Wang, Shiann-Rong Kuang, and Shish-Chang Liang, "High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19 , No. 1, pp. 52–60, January 2011.

· Shiann-Rong Kuang, Jiun-Ping Wang, and Hua-Yi Hong, "Variable-Latency Floating-Point Multipliers for Low-Power Applications," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 18, No. 10, pp. 1493-1497, October 2010.

· Shiann-Rong Kuang and Jiun-Ping Wang, "Design of Power-Efficient Configurable Booth Multiplier," IEEE Transactions on Circuits and Systems Part I: Regular Papers, Vol.57, No. 3, pp. 568-580, March 2010.

· Shiann-Rong Kung, Jiun-Ping Wang, and Cang-Yuan Guo, "Modified Booth Multipliers with a Regular Partial Product Array," IEEE Transaction on Circuits and Systems Part II:Express Briefs, Vol. 56, No. 5, pp. 404-408, May 2009.

· Yun-Lung Lee, Yung-Chao Chen, Jer-Min Jou, and Shiann-Rong Kung, "HW/SW Co-Design of a Multi-Threaded Java Virtual Machine", International Journal of Electrical Engineering, Vol. 15, No. 2, pp. 109-115, April 2008.

· Shiann-Rong Kung, Jiun-Ping Wang, "Design of power-efficient pipelined truncated multipliers with various output precision," IET Computers & Digital Techniques, Vol. 1, No. 2, pp. 129-136, March 2007.

· S.-R.Kuang and J.-P. Wang, "Low-error configurable truncated multipliers for multiply-accumulate applications," Electronics Letters, Vol. 42, No. 16, pp. 904-905, August 2006.

· Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau, and Ren-Der Chen, “Design of A Dynamic Pipelined Architecture for Fuzzy Color Correction,” IEEE Transactions on VLSI Systems, Vol. 10, No. 6,pp. 924-929, December 2002.

· Jer-Min Jou, Yeu-Horng Shiau, Pei-Yin Chen, and Shiann-Rong Kuang, “A Low Cost Gray Prediction Search Chip for Motion Estimation,” IEEE Transactions on Circuits & Systems Part I, Vol. 49, No. 7, pp. 928-938, July 2002.

· Shiann-Rong Kuang, Jer-Min Jou, Ren-Der Chen, and Yeu-Horng Shiau, “Dynamic Pipeline Design of an Adaptive Binary Arithmetic Coder,” IEEE Transactions on Circuits & Systems Part II, Vol. 48, No. 9, pp. 813-825, September 2001.

· Jer Min Jou, Shiann Rong Kuang, and Ren-Der Chen, “Design of Low-Error Fixed-Width Multipliers for DSP Applications,” IEEE Transactions on Circuits & Systems Part II, Vol. 46, No. 6, pp. 836-842, June 1999.

· Jer-Min Jou, Shiann-Rong Kuang, and Ren-Der Chen, “A New Efficient Fuzzy Algorithm for Color Correction,” IEEE Transactions on Circuits & Systems Part I, Vol. 46, No. 6, pp. 773-775, June 1999.

· Shiann-Rong Kuang, Jer-Min Jou, and Yuh-Lin Chen, “The Design of an Adaptive On-Line Binary Arithmetic Coding Chip,” IEEE Transactions on Circuits & Systems Part I, Vol. 45, No. 7, pp. 693-706, July 1998.

· Jer-Min Jou and Shiann-Rong Kuang, “Design of a low-error fixed-width multiplier for DSP applications,” Electronics Letters, Vol. 33, No. 19, pp. 1597-1598, 1997.

· Jer-Min Jou and Shiann-Rong Kuang, “A Library-Adaptively Integrated High Level Synthesis System,” Proceedings of NSC – Part A: Physical Science and Engineering, Vol. 19, No. 3, pp. 220-234, May 1995.

Patents

周哲民、鄺獻榮，”低誤差固定寬度(fixed-width)二補數平行乘法器”，中華民國專利第117044號，專利期間89/7/1～107/8/4。

周哲民、鄺獻榮，”一種使用於高時效電路設計之動態管線化方法”, 中華民國 專利第137795號，專利期間90/6/23～108/5/13。

Jer-Min Jou and Shiann-Rong Kuang, "Dynamic pipelining approach for high performance circuit design", United States Patent 6,594,814 (July 15,2003)